summaryrefslogtreecommitdiff
path: root/src/mainboard
AgeCommit message (Collapse)Author
2018-11-16mainboard: Add ASRock H81M-HDSTristan Corrick
Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with kernel 4.9. This board works quite well under coreboot. A list of what works and what doesn't can be found in the documentation part of this commit. The file `data.vbt` matches the VBT in the latest stable version of the vendor firmware (version 2.20). Change-Id: I53483bb9fa335e86e85dfc487fef03fce4b85e2a Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/29390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-11-16sb/intel/lynxpoint: Generate the ACPI FADT with a common functionTristan Corrick
The function `acpi_fill_fadt()` is based on that of sb/intel/bd82x6x. Tested on an ASRock H81M-HDS and a Google Peppy board, both using Linux 4.9 with `acpi=strict`. No ACPI errors or warnings appear in the kernel log. System reset, poweroff, and S3 suspend/resume continue to work. General improvements -------------------- - `fadt->preferred_pm_profile` is set based on the value of `CONFIG_SYSTEM_TYPE_LAPTOP` instead of being hardcoded. - Constants are used instead of magic values in more locations. - `fadt->gpe0_blk`, `fadt->gpe0_blk_len`, and `fadt->x_gpe0_blk` are set appropriately depending on whether the system uses Lynx Point LP or not. - Boards can indicate docking support in the FADT via the devicetree. Changes to existing Lynx Point boards ------------------------------------- - `header->asl_compiler_revision` changes from 1 to 0. - `fadt->model` is left at 0 instead of being set to 1. This field is only needed for ACPI 1.0 compatibility. - `fadt->flush_size` and `fadt->flush_stride` are set to 0. This is because their values are ignored, since `ACPI_FADT_WBINVD` is set in `fadt->flags`. - `fadt->duty_offset` is set to 0 instead of 1. None of the existing boards indicate support for changing the processor duty cycle (as `fadt->duty_width` is set to 0), so `fadt->duty_offset` does not currently need to be set. - Access sizes of registers are set. - On mb/intel/baskingridge, the pmbase is now read using the common function `get_pmbase()` instead of `pci_read_config16(...)`. - On mb/intel/baskingridge, the value of `fadt->x_gpe0_blk.bit_width` changes from 64 to 128. The correct value should be 128 (bits), to match `fadt->gpe0_blk_len`, which is set to 16 (bytes). - On Lynx Point LP systems, the unused extended address `fadt->x_gpe0_blk` sets its address space ID to be consistent with other unused extended addresses. Such a change should not alter the interpretation of the registers as being unused. Why not set them all to zero? Simply because the existing practice, in both coreboot and some other vendors' firmware, has them set in such a case. A diff of the FADT from a Google Peppy board is below: --- pre/facp.dsl 2018-10-30 20:14:52.676570798 +1300 +++ post/facp.dsl 2018-10-30 20:15:06.904381436 +1300 @@ -1,179 +1,179 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20180810 (64-bit version) * Copyright (c) 2000 - 2018 Intel Corporation * - * Disassembly of facp.dat, Tue Oct 30 20:14:52 2018 + * Disassembly of facp.dat, Tue Oct 30 20:15:06 2018 * * ACPI Data Table [FACP] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 4] Table Length : 000000F4 [008h 0008 1] Revision : 04 -[009h 0009 1] Checksum : 61 +[009h 0009 1] Checksum : 6E [00Ah 0010 6] Oem ID : "CORE " [010h 0016 8] Oem Table ID : "COREBOOT" [018h 0024 4] Oem Revision : 00000000 [01Ch 0028 4] Asl Compiler ID : "CORE" -[020h 0032 4] Asl Compiler Revision : 00000001 +[020h 0032 4] Asl Compiler Revision : 00000000 [024h 0036 4] FACS Address : 7BF46240 [028h 0040 4] DSDT Address : 7BF46280 -[02Ch 0044 1] Model : 01 +[02Ch 0044 1] Model : 00 [02Dh 0045 1] PM Profile : 02 [Mobile] [02Eh 0046 2] SCI Interrupt : 0009 [030h 0048 4] SMI Command Port : 000000B2 [034h 0052 1] ACPI Enable Value : E1 [035h 0053 1] ACPI Disable Value : 1E [036h 0054 1] S4BIOS Command : 00 [037h 0055 1] P-State Control : 00 [038h 0056 4] PM1A Event Block Address : 00001000 [03Ch 0060 4] PM1B Event Block Address : 00000000 [040h 0064 4] PM1A Control Block Address : 00001004 [044h 0068 4] PM1B Control Block Address : 00000000 [048h 0072 4] PM2 Control Block Address : 00001050 [04Ch 0076 4] PM Timer Block Address : 00001008 [050h 0080 4] GPE0 Block Address : 00001080 [054h 0084 4] GPE1 Block Address : 00000000 [058h 0088 1] PM1 Event Block Length : 04 [059h 0089 1] PM1 Control Block Length : 02 [05Ah 0090 1] PM2 Control Block Length : 01 [05Bh 0091 1] PM Timer Block Length : 04 [05Ch 0092 1] GPE0 Block Length : 20 [05Dh 0093 1] GPE1 Block Length : 00 [05Eh 0094 1] GPE1 Base Offset : 00 [05Fh 0095 1] _CST Support : 00 [060h 0096 2] C2 Latency : 0001 [062h 0098 2] C3 Latency : 0057 -[064h 0100 2] CPU Cache Size : 0400 -[066h 0102 2] Cache Flush Stride : 0010 -[068h 0104 1] Duty Cycle Offset : 01 +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 [069h 0105 1] Duty Cycle Width : 00 [06Ah 0106 1] RTC Day Alarm Index : 0D [06Bh 0107 1] RTC Month Alarm Index : 00 [06Ch 0108 1] RTC Century Index : 00 [06Dh 0109 2] Boot Flags (decoded below) : 0003 Legacy Devices Supported (V2) : 1 8042 Present on ports 60/64 (V2) : 1 VGA Not Present (V4) : 0 MSI Not Supported (V4) : 0 PCIe ASPM Not Supported (V4) : 0 CMOS RTC Not Present (V5) : 0 [06Fh 0111 1] Reserved : 00 [070h 0112 4] Flags (decoded below) : 00008CAD WBINVD instruction is operational (V1) : 1 WBINVD flushes all caches (V1) : 0 All CPUs support C1 (V1) : 1 C2 works on MP system (V1) : 1 Control Method Power Button (V1) : 0 Control Method Sleep Button (V1) : 1 RTC wake not in fixed reg space (V1) : 0 RTC can wake system from S4 (V1) : 1 32-bit PM Timer (V1) : 0 Docking Supported (V1) : 0 Reset Register Supported (V2) : 1 Sealed Case (V3) : 1 Headless - No Video (V3) : 0 Use native instr after SLP_TYPx (V3) : 0 PCIEXP_WAK Bits Supported (V4) : 0 Use Platform Timer (V4) : 1 RTC_STS valid on S4 wake (V4) : 0 Remote Power-on capable (V4) : 0 Use APIC Cluster Model (V4) : 0 Use APIC Physical Destination Mode (V4) : 0 Hardware Reduced (V5) : 0 Low Power S0 Idle (V5) : 0 [074h 0116 12] Reset Register : [Generic Address Structure] [074h 0116 1] Space ID : 01 [SystemIO] [075h 0117 1] Bit Width : 08 [076h 0118 1] Bit Offset : 00 -[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[077h 0119 1] Encoded Access Width : 01 [Byte Access:8] [078h 0120 8] Address : 0000000000000CF9 [080h 0128 1] Value to cause reset : 06 [081h 0129 2] ARM Flags (decoded below) : 0000 PSCI Compliant : 0 Must use HVC for PSCI : 0 [083h 0131 1] FADT Minor Revision : 00 [084h 0132 8] FACS Address : 000000007BF46240 [08Ch 0140 8] DSDT Address : 000000007BF46280 [094h 0148 12] PM1A Event Block : [Generic Address Structure] [094h 0148 1] Space ID : 01 [SystemIO] [095h 0149 1] Bit Width : 20 [096h 0150 1] Bit Offset : 00 -[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[097h 0151 1] Encoded Access Width : 02 [Word Access:16] [098h 0152 8] Address : 0000000000001000 [0A0h 0160 12] PM1B Event Block : [Generic Address Structure] [0A0h 0160 1] Space ID : 01 [SystemIO] [0A1h 0161 1] Bit Width : 00 [0A2h 0162 1] Bit Offset : 00 [0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] [0A4h 0164 8] Address : 0000000000000000 [0ACh 0172 12] PM1A Control Block : [Generic Address Structure] [0ACh 0172 1] Space ID : 01 [SystemIO] [0ADh 0173 1] Bit Width : 10 [0AEh 0174 1] Bit Offset : 00 -[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0AFh 0175 1] Encoded Access Width : 02 [Word Access:16] [0B0h 0176 8] Address : 0000000000001004 [0B8h 0184 12] PM1B Control Block : [Generic Address Structure] [0B8h 0184 1] Space ID : 01 [SystemIO] [0B9h 0185 1] Bit Width : 00 [0BAh 0186 1] Bit Offset : 00 [0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] [0BCh 0188 8] Address : 0000000000000000 [0C4h 0196 12] PM2 Control Block : [Generic Address Structure] [0C4h 0196 1] Space ID : 01 [SystemIO] [0C5h 0197 1] Bit Width : 08 [0C6h 0198 1] Bit Offset : 00 -[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C7h 0199 1] Encoded Access Width : 01 [Byte Access:8] [0C8h 0200 8] Address : 0000000000001050 [0D0h 0208 12] PM Timer Block : [Generic Address Structure] [0D0h 0208 1] Space ID : 01 [SystemIO] [0D1h 0209 1] Bit Width : 20 [0D2h 0210 1] Bit Offset : 00 -[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D3h 0211 1] Encoded Access Width : 03 [DWord Access:32] [0D4h 0212 8] Address : 0000000000001008 [0DCh 0220 12] GPE0 Block : [Generic Address Structure] -[0DCh 0220 1] Space ID : 00 [SystemMemory] +[0DCh 0220 1] Space ID : 01 [SystemIO] [0DDh 0221 1] Bit Width : 00 [0DEh 0222 1] Bit Offset : 00 [0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] [0E0h 0224 8] Address : 0000000000000000 [0E8h 0232 12] GPE1 Block : [Generic Address Structure] [0E8h 0232 1] Space ID : 01 [SystemIO] [0E9h 0233 1] Bit Width : 00 [0EAh 0234 1] Bit Offset : 00 [0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] [0ECh 0236 8] Address : 0000000000000000 Change-Id: I9638bb5ff998518eb750e3e7e85b51cdaf1f070e Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/29387 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16mb/google/poppy/variant/atlas: I2C: run trackpad at 1MHzCaveh Jalali
With this change, coreboot thinks we're running at 1MHz: DW I2C bus 2 at 0xd1133000 (1000 KHz) Elan eKT3644 IC Specification (trackpad) requires: Low Time larger than 500ns (61 * 8.3ns = 506ns). High Time larger than 260ns (32 * 8.3ns = 265ns), Data Hold_time larger than 0ns. Start Condition Hold time larger than 250ns. Rise/Fall time of less than 120ns. HCNT controls both High Time and Start Condition Hold time. LCNT controls Low Time. SDA_HOLD controls Data Hold Time. P2 Atlas "Rise time" is 90ns and "Fall time" is 32ns and tuned using resistors on the board and must be considered when adjusting any of the parameters since these times are all measured at 30 or 70% of base and peak voltages (0v/1.8v). The eKT3644 requirements are met with LCNT=69, HCNT=33, SDA_HOLD=20 which yields the SCL at around 950KHz - suboptimal but compliant. Lower LCNT or HCNT results in "lost arbitration" errors or not complying with eKT3644 requirements. Verified by gaggery.tsai@intel.corp-partner.google.com. Scope shots posted here: https://b.corp.google.com/issues/78601949#comment177 BUG=b:78601949 BRANCH=none TEST=Farzam provided test points on track pad for SCL/SDA/GND. Waveforms measured with oscilloscope and screen shots attached to bug (comment #177, #155, #100). Operate trackpad/touchscreen Review dmesg (kernel) output for correct speed, parameters, and no errors (e.g. "lost arbitration" or "host controller timeout") Change-Id: Iaf42ba7b8818b7cd9c8dcc657823dac705659d38 Signed-off-by: Caveh Jalali <caveh@chromium.org> Signed-off-by: Grant Grundler <grundler@chromium.org> Tested-by: gaggery.tsai@intel.corp-partner.google.com Tested-by: grundler@chromium.org Reviewed-on: https://review.coreboot.org/29553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
2018-11-16mb/intel/whlrvp: Enable HDA controller driverLijian Zhao
Enable HDA controller coreboot driver for Whiskey Lake RVP platform on top of common code. BUG=N/A TEST=Build and boot up on whiskey lake rvp board, comfirm audio playback is working. Change-Id: I7daf1c741b92ff59b9cb4030d218e9c1054c4b79 Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com> Reviewed-on: https://review.coreboot.org/28781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2018-11-16mb/intel/cougar_canyon2: Fix SMBIOS_ENCLOSURE_TYPE symbolElyes HAOUAS
Change-Id: I9f4640ef040dc6a1d39ecb8b3378266e4dd5cec9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16mb/msi/ms9652_fam10: Remove unused VAR_MTRR_HOLEElyes HAOUAS
Change-Id: Ibbc010c9550c0a50b1e913e198f9b575107572fb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16mb/{google/cyan,intel/strago}: Remove unused DYNAMIC_VNN_SUPPORTElyes HAOUAS
Change-Id: I4d0df30255d006c0399dde1b3ba8ee513d98dc0a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16src/mainboard: Remove unused "HW_MEM_HOLE_SIZE_AUTO_INC"Elyes HAOUAS
Change-Id: I10e89de270a20dbd28647e8b0f8a2425c515b350 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-11-16mb/{lenovo,roda}: Remove DISPLAY_DEVICE_2_IS_LCD_SCREEN macroPeter Lemenkov
This macro is no longer used since commit dd2bc3f8 with Change-Id I556769e5e28b83e7465e3db689e26c8c0ab44757 ("igd.asl rewrite"). Change-Id: Iabf927d8462673cb96851c01318d826d4c422e0d Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
2018-11-16mb/google/kalista: Disable EC-EFSDaisuke Nojiri
Only input from the BJ port is wired to VSYS on Kalista. VBUS from USB-C is for output only. In other words, Kalista is a source only device from a USB/PD perspective. This patch disables EC-EFS, which would be needed for the EC to jump to RW to get PD power before the AP boots. Kalista will be always supplied enough power to boot the AP through the BJ port. CQ-DEPEND=CL:1330171 BUG=b:118386511 BRANCH=none TEST=Boot Fizz. Verify normal boot, soft sync, recovery mode work. Change-Id: Icd18662ae1e76f35eb9bcd521b1951aacc713252 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/29564 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16src: Remove unneeded include <lib.h>Elyes HAOUAS
Change-Id: I801849fb31fe6958e3d9510da50e2e2dd351a98d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16src: Get rid of duplicated includesElyes HAOUAS
Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-16mb/google/poppy/variants/nautilus: Control GPP_D0 in 2nd SKU onlySeunghwan Kim
GPP_D0 is NC in 1st SKU board design, so we should control GPP_D0 for only 2nd SKU. BUG=none BRANCH=poppy TEST=emerge-nautilus coreboot Change-Id: Ifd85693c9155ed960f0c794d4b83fe8863b77134 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/29631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-16mb/google/poppy/variant/nocturne: Configure GPP_E1 for WLAN_WAKE_LNick Vaccaro
The GPP_E1 gpio was incorrectly being defined as a no-connect. Configure GPP_E1 for the WLAN_WAKE_L signal as per the schematic. BUG=b:119508897 TEST=Build and flash nocturne, boot nocturne and 1) Verify nocturne can successfully suspend/resume from S3 and S0ix. 2) Verify wake from wlan wakes device from S3 and S0ix. To do so, a) as root, execute "iw phy phy0 wowlan enable disconnect" on DUT b) connect DUT to mobile hotspot c) sleep device via "powerd_dbus_suspend" d) turn off hotspot, verify DUT wakes from S0ix e) enable hotspot again f) connect DUT to hotspot g) sleep DUT via "sudo echo mem > /sys/power/state" h) turn off hotspot, verify DUT wakes from S3 Change-Id: I4efb4f6d601e172ae4807901e3bd4c9954319f80 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/29630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-16src: Remove unneeded include <pc80/keyboard.h>Elyes HAOUAS
Change-Id: I0dcdfb1fa782c7936a19de11adcf17387f49d9db Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-16mb/*/*/Kconfig: Don't specify devicetree path if default val usedPeter Lemenkov
Change-Id: I3d77a625c5ece7b7ea5476fe0bd42829d1fc72c4 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29625 Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16mb/*/*/Kconfig: Use CONFIG_VARIANT_DIR for devicetreePeter Lemenkov
Change-Id: Ic9620cfa1630c7c085b6c244ca80dc023a181e30 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-16mb/cavium/cn8100_sff_evb: adjust fmapMarcello Sylvester Bauer
Adjust the default fmap description file. Tested on real hardware. Change-Id: I46165eb27314a500187bcd24e3e201cf6a3175e7 Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com> Reviewed-on: https://review.coreboot.org/29596 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16mb/lenovo/x60/dsdt: Remove unused includePeter Lemenkov
Tested - builds fine with this patch. Change-Id: I4666a8c9dd0e03ee32770844019dfc032e07e460 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
2018-11-16siemens/mc_apl4: Clean up ramstageMario Scheithauer
Currently, there is nothing for this mainboard to do in ramstage. Change-Id: Id74a5f3f0a0583dc6bc81044913b8bb83d3b0b93 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-16siemens/mc_apl4: Overwrite swizzle data for LPDDR4Mario Scheithauer
This mainboard is equipped with LPDDR4 modules. The corresponding memory swizzle data must be set for this purpose. Change-Id: I4017de0713f0df5e614086912fc39d8eb6562702 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Uwe Pöche <uwe.poeche@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-16mb/google/octopus: override smbios manufacturer name from CBIWisley Chen
BUG=b:118798180 TEST=emerge-octopus Change-Id: I241a76e3b55ad721c6c0176462c310bcca6b3c5d Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/29503 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-15ec/google/chromeec/acpi: Rename EC_ENABLE_TABLET_EVENT configKarthikeyan Ramasubramanian
Rename EC_ENABLE_TABLET_EVENT config as EC_ENABLE_MULTIPLE_DPTF_PROFILES since it aligns with the use-case. BUG=b:118149364 BRANCH=None TEST=Ensured that the expected DPTF table are loaded in different modes (base attached/detached and clamshell/360-flipped) on Soraka and Nautilus. Change-Id: If147f1c79ceaaed00e17ec80ec6c912a8f7a8c2e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/29261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-11-15src/mainboard/google: Remove defining EC_ENABLE_TABLET_EVENT configKarthikeyan Ramasubramanian
Remove defining EC_ENABLE_TABLET_EVENT configuration from the boards where it is not required. BUG=b:118149364 BRANCH=None TEST=Build Change-Id: Iee70192916ac6c53bb27b7f73f3ad6d069afd030 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/29637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-14mb/emulation/qemu-i440fx|q35: Fix stack sizePatrick Rudolph
Current implementation works by luck as DCACHE area is actually RAM and stack can grow and use that RAM outside of the area. * Set DCACHE_BSP_STACK_SIZE to 0x4000. * Add an assert to make sure it is set to a sane value on all platforms. Change-Id: I71f9d74d89e4129cdc4a850acc4fc1ac90e5f628 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/29611 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-13google/grunt: Update Samsung K4A8G165WC-BCTD SPD Module Part NumberKevin Chiu
Correct SPD Module Part Number to "K4A8G165WC-BCTD" from "M471A5244CB0-CTD". BUG=b:119400832 BRANCH=master TEST=emerge-grunt coreboot chromeos-bootimage mosys memory spd print all 0 | DDR4 | SO-DIMM 0 | 1-78: Samsung | 00000000 | K4A8G165WC-BCTD 0 | 4096 | 1 | 64 0 | DDR4-1333, DDR4-1600, DDR4-2400 Change-Id: I29505d3eece2283579499a0afc424c4a28017fa5 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/29557 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-13google/grunt/aleena: Update H1/TP/TS i2c timingsLucas Chen
After adjustment on aleena EVT Audio: 390.0 KHz H1: 390.0 KHz TP: 399.8 KHz TS: 399.8 kHz BUG=b:116306959 BRANCH=master TEST=emerge-grunt coreboot, scope measuring. Change-Id: I6f621508ce2dbb1b9dcdf529ac35afc80d485f53 Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-11-13mb/google/sarien: Enable EC _PTS/_WAK methodsDuncan Laurie
Enable the option to have the system level _PTS/_WAK methods call the EC provided methods when they are invoked by the OS. Verified on sarien board by inspecting dsdt.dsl: Method (_PTS, 1, NotSerialized) // _PTS: Prepare To Sleep { DBG0 = 0x96 \_SB.PCI0.LPCB.EC0.PTS (Arg0) } Method (_WAK, 1, NotSerialized) // _WAK: Wake { DBG0 = 0x97 \_SB.PCI0.LPCB.EC0.WAK (Arg0) Return (Package (0x02) { Zero, Zero }) } Change-Id: I52be1c1cd7adae9ad317a51868735eb87a410549 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-13mb/cannonlake: Remove SmbusEnable from devicetreeDuncan Laurie
Remove the SmbusEnable parameter from all Cannon Lake mainboards. Instead this will be determined by the enable state of the SMBUS PCI device. Change-Id: I7ece6768da4c517747af12a07012583575816ae1 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-13soc/intel/icelake: Update GPIOs for Icelake SOCAamir Bohra
This implementation updates the GPIO pins, communities and group mapping. Change details: 1. Update 5 GPIO community includes 11 GPIO groups GPIO COM 0 GPP_G, GPP_B, GPP_A GPIO COM 1 GPP_H, GPP_D, GPP_F GPIO COM 2 GPD GPIO COM 4 GPP_C, GPP_E GPIO COM 5 GPP_R, GPP_S 2. Update GPIO IRQ routing. 3. Add GPIO configuration for iclrvp board. Change-Id: I223abacc18f78631a42f340952f13d45fa9a4703 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/29495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2018-11-13mb/opencellular/rotundu: Remove unused CACHE_ROM_SIZE_OVERRIDEElyes HAOUAS
Change-Id: If77c23fc5d440fe9181e4aae72ffff8ddaa716b6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-11-12mb/google/octopus/var/bobba: Configure EC_SYNC IRQ as level-triggeredFurquan Shaikh
This change updates the configuration of EC_SYNC IRQ to be level triggered to match the EC behavior. Change-Id: I8e3cb2ae8016ea183d9067697aa5d4b9caa2d07e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2018-11-12mb/emulation/qemu-i440fx|q35: Switch to C_ENVIRONMENT_BOOTBLOCKPatrick Rudolph
Useful for testing stuff in C_ENVIRONMENT_BOOTBLOCK, like VBOOT with separate verstage. Changes: * Use symbols to set up CAR and STACK * Zero CAR area * Move BIST failure checking to cpu folder * Rename functions where necessary Tested: * qemu-2.11.2 machine pc * qemu-2.11.2 machine q35 Test result: * BIST error reporting is still working. * Console starts in bootblock * SeaBios 1.11.2 as payload is still working Change-Id: Ibf341002c36d868b9b44c8b37381fa78ae5c4381 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/29578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-12mb/emulation/qemu-i440fx|q35: Get rid of unused headersPatrick Rudolph
Change-Id: I3cf0e4ef5b090d15ad823747fcf9219644e130fc Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/29577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-11-12mb/*/*: Harmonise FD and devicetree on boards featuring ICH7Arthur Heymans
On some boards the devicetree and Function Disable register did not match. In this case the FD values are put in the devicetree as these were the values that were actually used in practice. A complete devicetree will make it easier to automatically disable devices in ramstage. Change-Id: I1692ca5f490ea84e2fc520d3f66044ad7514f76e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-11-12intel/i945: Factor out ram init time stampsPaul Menzel
Instead of having the code for the RAM init time stamps in each mainboard’s `romstage.c`, factor it out to the northbridge code, done in commit 771328f7 (intel/i945: add timestamps in romstage). Change-Id: Ibb699a1fea2f0b1f3c6564d401542d2fb3249f5a Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/17994 Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-12mb/emulation/qemu-i440fx/Makefile.inc: Fix "No newline at end of file"Elyes HAOUAS
Change-Id: I79e9b95059f16c53767c89cfaef1e89182be9c62 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29583 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-12siemens/mc_apl4: Enable SDCARDMario Scheithauer
This mainboard also has a SD slot. Change-Id: Id56bc1be60ec8c2be0e5543d1d8851610b7248e0 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl4: Remove external RTC from I2C0Mario Scheithauer
This mainboard also has an external RTC chip, but not on this bus. The topic is currently in clarification and will be published with a later patch. In a first step we enable all I2C busses. Change-Id: I9ec9631ed15ab30cc6a4594531521f4a1419ad00 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl4: Enable all PCIe root portsMario Scheithauer
Enable all PCIe root ports for this mainboard. Change-Id: I7f6feb2f0d4c45f32d9454838e67e1a244b2712b Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl4: Remove reduced clock rate for I2C0Mario Scheithauer
There is no device on I2C0 which requires a lower clock rate. Change-Id: Ib7c4e3251545b2d32368dd56206e3b4844a24800 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl4: Disable CLKREQ of PCIe root portsMario Scheithauer
All PCIe root ports of this mainboard do not have an associated CLKREQ signal. Therefore the ports are marked with "CLKREQ_DISABLED". Change-Id: I834b3b0c77223d81c950e27ccfff8e9aeece2aa4 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl3: Disable PCI clock outputs on XIO bridgesMario Scheithauer
On this mainboard there are legacy PCI device, which are connected to different PCIe root ports via PCIe-2-PCI bridges. This patch disables the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges. Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl3: Set Full Reset Bit into Reset Control RegisterMario Scheithauer
This mainboard provides customer hardware reset button. A feature of this button is that it holds the APL in reset state as long as the reset button is pressed. After releasing the reset button the APL should restart again without the need for a power cycle. When Bit 3 in Reset Control Register (I/O port CF9h) is set to 1 and then the reset button is pressed the PCH will drive SLP_S3 active (low). Change-Id: Ib842f15b6ba14851d7f9b1b97c83389adc61f50b Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl3: Set bus master bit for on-board PCI deviceMario Scheithauer
There is an on-board PCI device where bus master has to be enabled in PCI configuration space. As there is no need for a complete PCI driver for this device just set the bus master bit in mainboard_final(). Change-Id: I1ef4a7774d4ca75c230063debbc63d03486fed6f Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl3: Remove the correction of the Tx signal for SATAMario Scheithauer
For this mainboard the correction of transmit voltage swing from SATA interface is not necessary. Change-Id: I900d0d44b88585c223182d85c78cf3ff1e3e9159 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-12siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devicesMario Scheithauer
On this mainboard there is a legacy PCI device, which is connected to the PCIe root port via a PCIe-2-PCI bridge. This device only supports legacy interrupt routing. For this reason we have to adjust the PIR6 register (0x314c) which is responsible for PCIe device 13h and 14h. This means that the interrupt routing will also be the same for both PCIe devices. The bridge is connected to PCIe root port 2 and 3 over two lanes (Device 13.0 and 13.1). The following routing is required: INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#->PIRQC# Change-Id: I5028c26769a2122b1c609ad7789c9949e3cb7a87 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29513 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-12mb/google/octopus/variants/fleex: Set up tcc offset for fleexJohn Su
Change tcc offset from 0 to 10 for fleex. Refer to b:117789732#1 BUG=b:117789732 TEST=Match the result from TAT UI Change-Id: I481526ab10a16a33fe0cf9528b52b8524e012451 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-11mb/emulation/qemu-i440fx|q35: Link memory.cPatrick Rudolph
Link memory.c instead of including it. Change-Id: I2bc461b13332ec5885c33c87828a5fd023f8e730 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/29574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-11-10mb/lenovo/t400: Improve docking codePatrick Rudolph
* Remove dead code * Add support for types 2504 and 2505 * Print dock info at romstage entry * Improve dock disconnect for type 2505 * Move defines into dock.h for future ACPI code * Reduce timeouts according to spec to decrease boot time on error * Fix no docking detection (reduces boot time by 1 second) * Configure GPIO LDN before reading GPIOs * Use Kconfig values instead of fixed defines * Add documentation Tested on Lenovo T500 with docking 2504 and 2505. Change-Id: Ic4510ffadc67da95961cecd51a6d8ed856b3ac99 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/29418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-11-09mb/google/kahlee/variants/liara: Decrease eDP adjust time to 20 msChris Wang
Add 20ms adjust timing for edp panel in devicetree. BUG=b:118011567 TEST=verify panel sequences by ODM. Change-Id: Iab46f6fc653047a1ec6e8528eefa0999d7019690 Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29473 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-09mb/google/kahlee: Tune eDP panel initialization timeChris Wang
1. Add two parameters for panel initialization timing. > lvds_poseq_varybl_to_blon > lvds_poseq_blon_to_varybl 2. The BL_PWM is controlled by APU_EDP_BKLTEN_L/APU_DP_VARY_BL/ EDP_BKLTEN_L, so move APU_EDP_BKLTEN_L to early init stage, and be enabled depends on SKU, thus we can control the delay time by config APU_DP_VARY_BL. BUG=b:118011567 TEST=emerge-grunt coreboot. Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-11-09mb/intel/icelake_rvp: Move CNVi ASL entry from static DSDT to dynamic SSDT ↵Subrata Banik
generation This changes uses drivers/intel/wifi chip for CNVi device to ensure that: 1. Correct device name shows in ACPI name space 2. Correct wake up shows in cat /proc/acpi/wakeup 3. Remove cnvi.asl from soc/intel/icelake Change-Id: I21d3818ac9e384b0dbaa330d231022bdb8b8a547 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/29507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2018-11-08mb/google/sarien: Set runtime IRQs to reset on PLTRSTDuncan Laurie
GPIOs that use GPI_APIC setting with DEEP can cause an IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic reset over PLTRST to prevent IRQ strom after S3 resume. For sarien/arcada these are all runtime IRQs only, not wake capable. Change-Id: Iec3706a3b47b54abbacd06081910f389979c330f Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-08mb/google/sarien: Disable eSPI when ACPI is enabledDuncan Laurie
Select the option to disable eSPI when ACPI is enabled so the EC is unable to assert an SMI when booted into the OS. There is a kernel driver that implements the same mailbox interface so it cannot also be used by the SMI handler. Change-Id: I8bafc749f22aed5595e19e773762ee8b038950b9 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-08mb/google/poppy/variant/nocturne: configure SAR irqs to use PLTRSTNick Vaccaro
GPIO's that use GPI_APIC setting with DEEP causes an IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic reset over PLTRST to prevent IRQ storm after S3 resume and hence configuring GPP_D9 and GPP_D10 to use PLTRST. BUG=b:119202293 TEST=none Change-Id: I98d71100f28fb9bae05db3fb7d9afcb3f81beb43 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/29538 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-08mb/google/poppy/variant/nocturne: use PLTRST for GPP_C11Nick Vaccaro
GPP_C11 (FPMCU_INT_L) was set to DEEP, causing problems with S3. Changed GPP_C11 configuration to use PLTRST instead. BUG=b:114196791 TEST=Build, flash, boot nocturne, log in to kernel and execute the following two commands and verify it passes : echo 0 > /var/lib/power_manager/suspend_to_idle && restart powerd sudo suspend_stress_test -c 2 Change-Id: I008532fce963c51a435378001440ac72b5ebfffc Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/29429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-08mb/google/octopus/variants/baseboard: Improve cold boot and S3 resumeJohn Zhao
FSP 2.0.7.1 provides UPD interface to execute IPC command. Configure PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay from default 100ms to 10ms to improve cold boot and S3 resume performance. BUG=b:118676361 CQ-DEPEND=CL:*703187 TEST=Verified system_resume_firmware_ec time reduction. Change-Id: I41b8268c752573d828e31a1d94d3f175aa3cc145 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/29485 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-08mb/google/poppy/variants/nami: add the hynix memory partsRen Kuo
add the memory parts as ram id 10: hynix_dimm_H5ANAG6NAFR-UHC BUG=b:113983573 BRANCH=Nami TEST=emerge-nami coreboot chromeos-bootimage Change-Id: I137259b88f39779768a58959a2dcc565645eee6d Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-08src/mb/pcengines/apu2/romstage.c: Allow coreboot console output on COM2Michał Żygowski
This change allows to redirect coreboot console output to COM2 by setting appropriate UART index in Console menu in Kconfig. Change is helpful for users which would like to use COM1 port for other purposes, because COM1 is the only port with hardware flow control. Change-Id: I39f88d7e7794f603775a985afe07fef349172e5f Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/29255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-11-07siemens/mc_apl4: Add new mainboard variant mc_apl4Mario Scheithauer
This mainboard is based on mc_apl1. In a first step, it concerns a copy of mc_apl1 directory with minimum changes. Special adaptations for mc_apl4 mainboard will follow in separate commits. Change-Id: I3dfdccc8198f3a23a45d319ede6080803a46f7f6 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-11-07siemens/mc_apl2: Adjust GPIO settings for mc_apl2Mario Scheithauer
This mainboard variant requires GPIO adaptations to match the hardware. Change-Id: I16387358d6c6fa15efd16f7ba7f6b89740477e9d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-07mb/{lenovo/x201,packardbell/ms2290}/romstage: Fix commentsPeter Lemenkov
RCBA address numbers in comments looks wrong and confusing. Let's fix them. This is a cosmetic change since no actual data is added or removed. Change-Id: I0e521acdac17959586bc0af7d8a2f7182f1e6721 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-11-07mb/lenovo/*/*: Fix non-local header treated as localPeter Lemenkov
See also commit 4ad1446b with Change-Id I036208a111d009620d8354fa9c97688eb4e872ad ("Fix non-local header treated as local"). Change-Id: Idea19b52198e6f46b0da6022558a46246a52f2e7 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29501 Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-07mb/lenovo/x201: Remove unnecessary include - delay.hPeter Lemenkov
Change-Id: Ia997c5188aef0c18d871658209c2d5f718ee2a19 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-07mb/lenovo/x201/gpio: Use reset structurePeter Lemenkov
This structure was defined but never used. Let's use it. Change-Id: I73baf428a7300e64fa486699e82ef62c6a53ea60 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-11-07siemens/mc_apl3: Disable I2C7 over devicetreeMario Scheithauer
Disable I2C7 because there is no device connected. Change-Id: Ie9877d40b06f4a849163a873fd308ff03995fcdc Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-07siemens/mc_apl3: Enable all PCIe root portsMario Scheithauer
Enable all PCIe root ports for this mainboard. Change-Id: I62c7ba5048b4c2288bb502a78b9621edda333f2a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-11-07siemens/mc_apl3: Remove reduced clock rate for I2C0Mario Scheithauer
There is no device on I2C0 which requires a lower clock rate. Change-Id: Ib9ad4d9026267d2079e95245994d84c163b28dbb Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-11-07siemens/mc_apl3: Disable CLKREQ of PCIe root portsMario Scheithauer
All PCIe root ports of this mainboard do not have an associated CLKREQ signal. Therefore the ports are marked with "CLKREQ_DISABLED". Change-Id: I59c1132c6d273ccefeb1be6243577e1ae5064ef4 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-11-07siemens/mc_apl3: Adjust GPIO settings for mc_apl3Mario Scheithauer
This mainboard variant requires GPIO adaptations to match the hardware. Change-Id: I4ba475e7d387f46ed5f41b7a691c7933edbc50c5 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-11-07mb/google/sarien: Add sku_id functionDuncan Laurie
This change adds a sku_id() function that returns a static value to differentiate the sarien and arcada boards. Change-Id: I1fecc675573a6aece7188aae9370733068d45dbf Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29486 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-07mb/google/fizz: Comment variant names in KconfigDavid Wu
Refer to CL:1043916 BUG=none BRANCH=none TEST=none Change-Id: I3fbbbcac334646f68b8b9fd38fbb529d9e833581 Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-07mb/{intel/google}: Move CNVi ASL entry from static DSDT to dynamic SSDT ↵Subrata Banik
generation This changes uses drivers/intel/wifi chip for CNVi device to ensure that: 1. Correct device name shows in ACPI name space 2. Correct wake up shows in cat /proc/acpi/wakeup 3. Remove cnvi.asl from soc/intel/cannonlake Change-Id: Ic81de2dce6045ced913766790a40ed19119f5118 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/29399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-05mb/google/poppy/variants/nami: Enable FP MCUShelley Chen
Some variants of nami will have a fingerprint MCU. BUG=b:118503113 BRANCH=Nami TEST=None (build and boot, but no hw yet) Change-Id: I446dc09cdf7f84a801723cb403d2de80e0997c65 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/29297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-05mb/asus/p5qc: Fix spelling of MarvellJonathan Neuschäfer
Marvell is the chip company, Marvel makes comic books. Change-Id: I437ac0d4fc706fbb62a0a74ca74a197dba4499fb Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/29347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-11-05mb/google/sarien: Enable WWAN detectionLijian Zhao
WWAN start-up control requires RESET# assert after FULL_CARD_POWER_OFF# set to high more than 10 ms, so force RESET#(GPP_D21) to low at bootblock stage to match the sequence. BUG=N/A TEST=Boot up Sarien/Arcada board, check WWAN get detected as USB devices through lsusb. Change-Id: I36eb841a2e8f2b36771d20577314a7451fbee133 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/29430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-11-05mb/google/fizz: Remove variant_cros_gpios from variantDavid Wu
This change removes the function defintions from variant so that the weak definition in baseboard can be used. Refer to CL:813944. BUG=none BRANCH=master TEST=Build and boot on DUT Change-Id: I561414fcc94e3c812bb88730df9b94e332c61781 Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-05mb/google/fizz/variants/karma: Update GPIO GPP_D9David Wu
Update GPP_D9 to fix audio jack can't detect issue. BUG=b:118393646 BRANCH=master TEST=Verify audio jack can auto detect. Change-Id: I87d24ed294c1ddc59bbd6ba9194c76d1f66413f3 Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-05mb/google/octopus/var/bobba: Define GPIO_134 as EC_SYNC_IRQEnrico Granata
Use GPIO_134 as the EC sync interrupt and provide this value to the embedded controller to be exported to the OS. BRANCH=none BUG=crbug:896347, b:118443377 CQ-DEPEND=CL:1298699 TEST=verify sensor events coming in on a reworked board with companion EC and kernel patches Change-Id: I41333cabe97bc8b0d59e19d84366f2ea2a59e026 Signed-off-by: Enrico Granata <egranata@chromium.org> Reviewed-on: https://review.coreboot.org/29278 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-05mb/google/poppy/variant/nocturne: add Nanya memory optionNick Vaccaro
Add option for Nanya NT6CL256T32CM-H1 part. Add comments to indicate total memory size for convenience. BUG=b:118624505 BRANCH=master TEST=none Change-Id: I82200e7b3d0a13295cb38f53ab576697ff8d302b Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/29341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-05src: Remove unneeded include <arch/ioapic.h>Elyes HAOUAS
Change-Id: Ic08b191ee4dbcc56eb482601aa268394545936ba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29292 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-05mainboard: Remove unneeded include <console/console.h>Elyes HAOUAS
Change-Id: Ib3aafcc586b1631a75f214cfd19706108ad8ca93 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29285 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-05amd: Fix non-local header treated as localElyes HAOUAS
Change-Id: I0668b73cd3a5bf5220af55c29785220b77eb5259 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29103 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-05src/mainboard: Remove irrelevant conditional statementElyes HAOUAS
Using a conditional statement to return 0 or 1 depending on a logic value is unnecessarily complex. Change-Id: I449ce2b71b72374de5ec4986f9cc9f91a67856ee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29265 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-04src/mb/asus/p5qc: Fix some mistakesAngel Pons
There are some small mistakes in these recently-added mainboards: - board_info.txt: Lists board socket incorrectly. - cmos.default: Loglevel was decreased some time ago. - devicetree.cb: Spelling mistake. - Kconfig: Mainboard name does not have a hyphen. Change-Id: I08d9b06e79683acd3994b84647bce401ed6741e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/29446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-02google/kukui: Add board id supportTristan Shieh
Get board id from AUXIN4 and RAM code from AUXIN3. BUG=b:80501386 BRANCH=none TEST=AUXIN4 is 0.074v and AUXIN3 is 0.212v on P0. AUXIN4 is 0.212v and AUXIN3 is 0.212v on P1. Change-Id: I50533e851d2fae66ae8c5e4e1aa36708d9058e94 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/29062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-02mb/google/sarien: Enable Wilco ECDuncan Laurie
The Sarien mainboard uses the newly added Wilco EC. - enable CONFIG_EC_GOOGLE_WILCO - add the device and host command ranges to the devicetree - have the mainboard SMI handlers call the EC handlers - add EC and SuperIO devices to the ACPI DSDT - call the early init hook for serial setup Change-Id: Idfc4a4af52a613de910ec313d657167918aa2619 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-11-02mb/google/sarien: Add Arcada variantDuncan Laurie
Add a variant of the Sarien board called Arcada. This is currently very similar to Sarien with differences in PCIe, USB, and GPIO usage. Change-Id: I432d2ba99558e960d4e775c809cc8bf6aa1a56bf Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29410 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-02mb/google/sarien: Add new mainboardDuncan Laurie
Sarien is a new board using Intel Whiskey Lake SOC. It also uses the newly added Wilco EC, enabled in a separate commit. Sarien is not a true reference board, it is just one variant of a very similar design. For that reason it is not considered the baseboard but rather a standalone variant. Change-Id: I2e38f617694ed2c2ef746ff8083f2bfd58cbc775 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-02mb/google/poppy/variants/nami: Enable radium touchscreen supportRen Kuo
Enable the radium touchscreen support BUG=b:117960394 BRANCH=master TEST= 1. emerge-nami coreboot chromeos-bootimage 2. boot up on ekko DUT to check touchscreen device by evtest /dev/input/event3: Raydium Touchscreen Change-Id: I16167d5d3ce6eac9d64832b52bb1945999a63a90 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29365 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-02mainboard/intel/icelake_rvp: Add ICL flash layout to support IFWI 1.6Aamir Bohra
Modify flash layout to match ICL-IFWI layout for early SoC PO support Flash Reg 0: Descriptor [0x0 - 0xFFF] Flash Reg 1: BIOS [0x400000 - 0xFFFFFF] Flash Reg 2: IFWI (consist of ME primary & secondary partition and PMC FW) [0x81000 - 0x3FFFFF] Flash Reg 8: EC (applicable for Intel RVP with internal EC support) [0x1000 - 0x80FFF] Change-Id: I462a384739b5972d9a59569ffdcadba7cdef6a81 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/29316 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-01sb/intel/common: Create a common implementation of `acpi_fill_madt()`Tristan Corrick
The function `acpi_fill_madt()` is identical among all the Lynx Point boards and sb/intel/bd82x6x, so share a common function between them. Earlier Intel platforms have similar implementations of this function. The common implementation might only need minor alterations to support them. Tested on an ASRock H81M-HDS and Google Peppy (variant of Slippy). No issues arose from this patch. Change-Id: Ife9e3917febf43d8a92cac66b502e2dee8527556 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/29388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-01sb/intel/lynxpoint: Add a common platform.asl fileTristan Corrick
The platform.asl file is copied from sb/intel/bd82x6x, and also matches the contents deleted from each mainboard's platform.asl. Tested on an ASRock H81M-HDS and a Google Peppy board (variant of Slippy). No issues arose from this patch. Change-Id: I539e401ce9af83070f69147526ca3b1c122f042c Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/29386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-01sb/intel/lynxpoint: Automatically generate the ACPI PCI routing tableTristan Corrick
This patch is based on a8a9f34e9b7b ("sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables") Tested on an ASRock H81M-HDS. The generated _PRT object looks correct, and the system doesn't show any issue when running. The following assignments occur: ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0 ACPI_PIRQ_GEN: PCI: 00:03.0: pin=0 pirq=0 ACPI_PIRQ_GEN: PCI: 00:14.0: pin=0 pirq=0 ACPI_PIRQ_GEN: PCI: 00:16.0: pin=0 pirq=0 ACPI_PIRQ_GEN: PCI: 00:1a.0: pin=0 pirq=0 ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=6 ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=0 ACPI_PIRQ_GEN: PCI: 00:1c.1: pin=1 pirq=1 ACPI_PIRQ_GEN: PCI: 00:1c.2: pin=2 pirq=2 ACPI_PIRQ_GEN: PCI: 00:1c.3: pin=3 pirq=3 ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=7 ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=1 pirq=3 ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=2 pirq=2 Also tested on a Google Peppy board. The following assignments occur: ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0 ACPI_PIRQ_GEN: PCI: 00:03.0: pin=0 pirq=0 ACPI_PIRQ_GEN: PCI: 00:14.0: pin=0 pirq=2 ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=6 ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=0 ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=3 ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=0 pirq=6 ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=1 pirq=2 ACPI_PIRQ_GEN: PCI: 00:1f.6: pin=2 pirq=1 A diff of the _PRT object for the Google Peppy board is below. The code used in the diff has been modified for clarity, but the semantics remain the same. To summarise the diff: * The disabled PCIe root ports are no longer included. * The LPC controller is no longer included, as it has no interrupt pin. The pins for the remaining LPC devices are each one less. Perhaps the original _PRT object was incorrect? * The SDIO device is no longer included, as it is disabled. * The Serial IO devices are no longer included, but that is due to a separate issue I am having with this system (the devices don't show up under Linux regardless of this patch). In short: their omission is not a fault of this patch. --- pre/_PRT +++ post/_PRT @@ -1,301 +1,157 @@ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { - Return (Package (0x12) + Return (Package (0x09) { Package (0x04) { 0x0002FFFF, Zero, Zero, 0x10 }, Package (0x04) { 0x0003FFFF, Zero, Zero, 0x10 }, Package (0x04) { 0x0014FFFF, Zero, Zero, 0x12 }, Package (0x04) { 0x001BFFFF, Zero, Zero, 0x16 }, Package (0x04) { 0x001CFFFF, Zero, Zero, 0x10 }, - Package (0x04) - { - 0x001CFFFF, - One, - Zero, - 0x11 - }, - - Package (0x04) - { - 0x001CFFFF, - 0x02, - Zero, - 0x12 - }, - - Package (0x04) - { - 0x001CFFFF, - 0x03, - Zero, - 0x13 - }, - Package (0x04) { 0x001DFFFF, Zero, Zero, 0x13 }, Package (0x04) { 0x001FFFFF, Zero, Zero, 0x16 }, Package (0x04) { 0x001FFFFF, One, Zero, 0x12 }, Package (0x04) { 0x001FFFFF, 0x02, Zero, 0x11 - }, - - Package (0x04) - { - 0x001FFFFF, - 0x03, - Zero, - 0x10 - }, - - Package (0x04) - { - 0x0015FFFF, - Zero, - Zero, - 0x14 - }, - - Package (0x04) - { - 0x0015FFFF, - One, - Zero, - 0x15 - }, - - Package (0x04) - { - 0x0015FFFF, - 0x02, - Zero, - 0x15 - }, - - Package (0x04) - { - 0x0015FFFF, - 0x03, - Zero, - 0x15 - }, - - Package (0x04) - { - 0x0017FFFF, - Zero, - Zero, - 0x17 } }) } Else { - Return (Package (0x12) + Return (Package (0x09) { Package (0x04) { 0x0002FFFF, Zero, ^LPCB.LNKA, Zero }, Package (0x04) { 0x0003FFFF, Zero, ^LPCB.LNKA, Zero }, Package (0x04) { 0x0014FFFF, Zero, ^LPCB.LNKC, Zero }, Package (0x04) { 0x001BFFFF, Zero, ^LPCB.LNKG, Zero }, Package (0x04) { 0x001CFFFF, Zero, ^LPCB.LNKA, Zero }, - Package (0x04) - { - 0x001CFFFF, - One, - ^LPCB.LNKB, - Zero - }, - - Package (0x04) - { - 0x001CFFFF, - 0x02, - ^LPCB.LNKC, - Zero - }, - - Package (0x04) - { - 0x001CFFFF, - 0x03, - ^LPCB.LNKD, - Zero - }, - Package (0x04) { 0x001DFFFF, Zero, ^LPCB.LNKD, Zero }, Package (0x04) { 0x001FFFFF, Zero, ^LPCB.LNKG, Zero }, Package (0x04) { 0x001FFFFF, One, ^LPCB.LNKC, Zero }, Package (0x04) { 0x001FFFFF, 0x02, ^LPCB.LNKB, Zero - }, - - Package (0x04) - { - 0x001FFFFF, - 0x03, - ^LPCB.LNKA, - Zero - }, - - Package (0x04) - { - 0x0015FFFF, - Zero, - ^LPCB.LNKE, - Zero - }, - - Package (0x04) - { - 0x0015FFFF, - One, - ^LPCB.LNKF, - Zero - }, - - Package (0x04) - { - 0x0015FFFF, - 0x02, - ^LPCB.LNKF, - Zero - }, - - Package (0x04) - { - 0x0015FFFF, - 0x03, - ^LPCB.LNKF, - Zero - }, - - Package (0x04) - { - 0x0017FFFF, - Zero, - ^LPCB.LNKH, - Zero } }) } } Change-Id: Id3f067cbf7c7d649fbbf774648d8ff928cb752a4 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/29381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-01mb/google/fizz/variants/karma: Rename kalista to karmaDavid Wu
Change the variant name from kalista to karma. According to the CL:1298319, the baseboard name is kalista and the board name is karma. BUG=none BRANCH=master TEST=emerge-kalista coreboot chromeos-bootimage Change-Id: Idea295cc14249721a6dc0fc4e2ef6470d43e16eb Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29314 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-01src: Add missing include <stdint.h>Elyes HAOUAS
Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-10-31Veyron: add Hynix H9CCNNNBKTMLBR-NTD ddr with RAMID '00Z1'Loop_Wu
Confirm with RK, H9CCNNNBKTMLBR-NTD uses this sdram config. sdram-lpddr3-hynix-4GB.inc BUG=b:117967129 BRANCH=master TEST=None Change-Id: I98afc33fd2cb61343be0dcdc007add75bee9c2af Signed-off-by: Loop_Wu <Loop_Wu@asus.com> Reviewed-on: https://review.coreboot.org/29366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-31reset: Finalize move to new APINico Huber
Move soft_reset() to `southbridge/amd/common/` it's only used for amdfam10 now. Drop hard_reset() for good. Change-Id: Ifdc5791160653c5578007f6c1b96015efe2b3e1e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 09:13:29 +0000