summaryrefslogtreecommitdiff
path: root/src/mainboard
AgeCommit message (Collapse)Author
2016-06-08veyron: Add exception_init() to romstageJulius Werner
I'm not even sure how this slipped through... looks like it had never been there in the first place. Anyway, on ARM exceptions should always be reinitialized in all stages to make sure the handlers are still around (especially in an OVERLAP_VERSTAGE_ROMSTAGE board like this one). Change-Id: Ic74ea1448d63b363f2ed59d9e2529971b3d32d9a Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15099 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-08gru: kevin: define GPIOs used on both platformsVadim Bendebury
The same GPIOs are used on both platforms, definitions are added an a new .h to make it easier to re-use them across the code. BRANCH=none BUG=chrome-os-partner:51537 TEST=panel backlight still enabled on Gru as before. The rest of the GPIOs are used in the upcoming patches. Change-Id: If06f4b33720ab4bf098d23fb91322bba23fe6e90 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: c587880 Original-Change-Id: I1a6c5b5beb82ffcc5fea397e8e9ec2f183f4a7e0 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/346219 Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-on: https://review.coreboot.org/15029 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08mainboard/intel/amenia: Enable VIRT_DEV_SWITCHRavi Sarawadi
Enable virtual dev switch config. BUG=None TEST= On Dev FW screen, press SPACE key to boot to normal mode Change-Id: I0fba36ed85025e4d17da106978dcc88497afee09 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/15080 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-08Intel/amenia: Make the device address more readableZhao, Lijian
Use central header file to include device address and interrupt line to avoid confusion. Change-Id: I9560031d9f6e12c665c8ae12f7028a67b6c8c904 Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Signed-off-by: Rohit Ainapure <rohit.m.ainapure@intel.com> Reviewed-on: https://chromium.devtools.intel.com/7248 Tested-by: N, Harshapriya <harshapriya.n@intel.com> Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com> Reviewed-on: https://chromium.devtools.intel.com/7580 Reviewed-by: N, Harshapriya <harshapriya.n@intel.com> Tested-by: Petrov, Andrey <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15083 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-08adi/rc-dff: Add Initial implementaionChris Ching
* Add ADI vendor Copy Intel Mohon Peak mainboard to ADI vendor. No functional changes, only string and ifdef names changed. Change-Id: I25a6d0ec549c79a8ff149d39f72648f625dc36fe Signed-off-by: Chris Ching <chingcodes@google.com> Reviewed-on: https://review.coreboot.org/14778 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-08mainboard/lenovo/x220: Clean up codeJan Tatje
thermal.h still has references to X230 in include guard since it seems to have been copied from that port. Code formatting changes in romstage.c. Change-Id: Id8bd931bed127036e8bb4ab604d9d6145f767e56 signed-off-by: Jan Tatje <jan@jnt.io> Reviewed-on: https://review.coreboot.org/15071 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-06-08mainboard/google/reef: Configure sd card pinsJagadish Krishnamoorthy
Since the sd card cmd, data, cd lines are configured as native mode, allow the native controller to control the termination. Configure SDCARD_CLK_FB which is used for calibrating the timing of the actual clock buffer. BUG==chrome-os-partner:53747 TEST=verify sd card detection Change-Id: I56611826afb4fb32fefa7f1e4ba19ca4f30ba578 Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://chromium-review.googlesource.com/348377 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15096 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-08lenovo/x60: add hda_verb.cArthur Heymans
This creates a config for the x60 audio based on values taken from vendor bios. The pin config is stored in (for linux 4.5 at least): /sys/class/sound/card0/hw*/init_pin_configs In the left column there is the pin number. In the right column there is the default configuration of that pin. (This has to be done while running the proprietary bios) More information on the sound card can be found in: /proc/asound/card0/codec#* This also hold the information of /sys/class/sound/ What is improved: - internal microphone is chosen by default - when jack is inserted it is chosen instead of internal speaker Before this had to be done manually in alsa or pulseaudio. TEST= check if internal microphone is used by default in pavucontrol if you are using pulseaudio. Plug in a jack with headphones and check if there is sound output through these and not the build-in speaker. Change-Id: Id3b700fd84905a72cc1f69e7d8bfa6145f231756 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/15063 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-07intel/amenia: Add asl code to enable google ChromeECShaunak Saha
This patch adds asl code to include support for Google ChromeEC. We need this to show the battery icon and notifications like charger connect/disconnect etc. BUG = 53096 TEST = Plug/Unplug AC Adapter multiple times and make sure the battery connected is charging properly. Change-Id: Id908f145789402573ea54fc4f15cf7a0e651ebf4 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/14987 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-06-07google/reef: Add asl code to enable google ChromeECShaunak Saha
This patch adds asl code to include support for Google ChromeEC. We need this to show the battery icon and notifications like charger connect/disconnect etc. BUG = 53096 TEST = Plug/Unplug AC Adapter multiple times and make sure the battery connected is charging properly. Change-Id: I06f48eda894418514c8ed0136500fff0efd12a35 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15069 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-06-07Kevin/Gru : Update Board ID table.jongpil19.jung
Add board id table as kevin/gru configuration. BUG=chrome-os-partner:53519 BRANCH=chromeos-2016.02 TEST=check boot on Kevin board. Change-Id: I30c16916f3cda0ac88d2ce5a922e936a405fcc89 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 16c7b5486befd73c3e31624970ba1c97e526676f Original-Change-Id: Ib69ed9dad8e1a9e08717545c6be19a90e0298c43 Original-Signed-off-by: jongpil19.jung <jongpil19.jung@samsung.com> Original-Reviewed-on: https://chromium-review.googlesource.com/345736 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15028 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-07rockchip: gru: update the hynix lpddr3 config to run at 928MHzShunqian Zheng
Update the DDR config and DRAM driver to allow running at up to 928MHz. Kevin config/clock rate are not being changed, but Gru now runs at 928 MHz. BRANCH=none BUG=chrome-os-partner:51537 TEST=booted Kevin and Gru to Linux prompt. Ran stressapptest for 10 min on Gru, Change-Id: I66c1a171d5c7d05b2878c7bc5eaa0d436c7a1be2 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 8baf0d82816a7ea1c4428e15caeefa2795d001f9 Original-Change-Id: I5e1d6d1025f10203da8f11afc3bbdf95f133c586 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/343984 Original-Reviewed-by: Stephen Barber <smbarber@chromium.org> Reviewed-on: https://review.coreboot.org/15027 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-05pcengines/apu1: Add SMBIOS SKU fieldKyösti Mälkki
Just the memory size, there is no strap to identify PCB revision. Change-Id: I65b2f5b0ac6930bead60ea0a551f13a6bcab24c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14997 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-06-04AGESA boards: Split dispatcher to romstage and ramstageKyösti Mälkki
The way dispatcher table is set up prevents linker from optimizing unused code away, we currently have raminit in ramstage. Optimize this manually by configuring AGESA_ENTRY booleans for romstage and ramstage separately. This will remove references in FuncParamsInfo and DispatchTable -arrays. All boards now include multi-core dispatcher, it has minimal footprint: AGESA_ENTRY_LATE_RUN_AP_TASK ACPI S3 support depends on HAVE_ACPI_RESUME being enabled: AGESA_ENTRY_INIT_RESUME AGESA_ENTRY_INIT_LATE_RESTORE AGESA_ENTRY_INIT_S3SAVE Disabled for all boards as it was not used: AGESA_ENTRY_INIT_GENERAL_SERVICES Change-Id: I7ec36a5819a8e526cbeb87b04dce4227a1689285 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14417 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-04gm45: enable setting all vram sizes from cmosArthur Heymans
Setting the size of the preallocated memory for the igd is done using a cmos parameter, gfx_uma_size. This was limited to a subset of all available sizes, that were already implemented elsewhere in the northbridge code. What this does is change the cmos parameter to 4 bits instead of 3 bits to accomodate all vram sizes. It also adds a sane default of 32mb that already was in place. The northbridge code that reads this cmos parameter is also changed for this new cmos settings. 352M is disabled since it causes issues on systems with 4GB or more ram. TEST: Build, flash target. Clear cmos by corrupting the checksum (nvramtool -c something). Set a desired value in gfx_uma_size using nvramtool. "dmesg | grep stolen" to see what is actually allocated. Change-Id: Ia6479d03f1abe6d0c94bd7264365505e8f8eaeec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/14900 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-06-04AGESA f12 f15: Add OEM customisationKyösti Mälkki
Follow-up on commits a5d72a3 and 53052fe for f12 and f15. OEM Hooks are not BiosCallOuts. Change-Id: Iab22b0d73282a5a1a5d1344397b4430c0ebb81b5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14888 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-03AMD boards: Drop comment on include fileKyösti Mälkki
The included file does not declare pm_ioread(), and the modified file does not call it either. Change-Id: I9723caf1062db23b4a3648e07c2dc4c02f862619 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14968 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-03aopen/dxplplusu: Disable HW scrubberKyösti Mälkki
See initialize_ecc() for the awful hack that got us around cache-as-ram being invalidated as we do ECC HW scrubbing. It once worked, but compiler nowadays puts more registers on the stack. Not much interest to try fix ECC for this particular board. Change-Id: Ie6a09e28b0af5bbf2d68af72f5d98c03df33c402 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15014 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-03rockchip: gru: enable eDP displayLin Huang
This patch enables eDP display by: o. setting HPD pinmux, backlight, vdd for eDP o. setting vop mode o. enabling VGA configs for edid BRANCH=none BUG=chrome-os-partner:51537 TEST=The dev screen is shown on kevin board Change-Id: If8b07307454daa88727d317cc208d6c97de07ad7 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: b1ad9337510f5437f691153dc68883edf273e4c7 Original-Change-Id: Id7006619b5be638b286a5402d892a5361ac1e430 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/340026 Original-Reviewed-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-on: https://review.coreboot.org/14858 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-03mainboard/intel/galileo: Add CREATE_BOARD_CHECKLISTLee Leahy
Select CREATE_BOARD_CHECKLIST to create the checklist for the Quark SOC and Galileo board. TEST=Build and run on Galileo Gen2. Change-Id: Ieb3e9a5a4c149cf160e11d44a515591b57fe5c83 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15004 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-03mainboard/intel/galileo: Set board versionLee Leahy
Return the correct board version in SMBIOS. TEST=Build and run on Galileo Gen2 Change-Id: I97ec7bcd475142eb90930152da0244a3c5d09634 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15041 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-03AGESA boards: Drop unused includeKyösti Mälkki
These files do not use definitions from OptionsIds.h. Also those definitions are required and already included for Ids.h. Change-Id: I149fcfe2ad72fe3d7390ee2043a86432aeae3f08 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14980 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-02google/reef: Select UART_FOR_CONSOLE for reefFurquan Shaikh
Change-Id: I714af8ab552dc1923a1b64e0c502d6c7b96dd444 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15044 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-02lenovo/t420: correct the eSATA portIru Cai
The eSATA port of Lenovo T420 is port 3. I've checked it on an iGPU model and a dGPU model. Change-Id: I64bcc887140c1634dd1475d29e97780a5128d0be Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/14632 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2016-06-02Gale board: Move TPM setup function to verstage.cKan Yan
TPM should be only be reset once in verstage. BUG=chrome-os-partner:51096 TEST=Depthcharge no longer shows TPM error. BRANCH=None Original-Signed-off-by: Kan Yan <kyan@google.com> Original-Commit-Id: 911bdaa83a05fa5c8ea82656be0ddc74e19064c3 Original-Change-Id: I52ee6f2c2953e95d617d16f75c8831ecf4f014f9 Original-Reviewed-on: https://chromium-review.googlesource.com/343537 Original-Commit-Ready: Kan Yan <kyan@google.com> Original-Tested-by: Kan Yan <kyan@google.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Change-Id: I8047b7ba44c604d97a662dbf400efc9eea2c7719 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14845 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2016-06-01mb/lenovo/T4xx: enable PEG devicePatrick Rudolph
Enable the PEG device in devicetree to expose the device if any. This is already default behaviour for T5xx series. Change-Id: I16bd253ca96c4cdaad8a829f6490cec9e2599b5f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14448 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-06-01drivers/lenovo: Add hybrid graphics driverPatrick Rudolph
Add a universal hybrid graphics driver compatible with all supported lenovo devices. Hybrid graphics allows to connect the display panel to either of one GPUs. As there are only two GPUs one GPIO needs to be toggled. In case the discrete GPU is activated the panel is routed to it. On deactivation the panel is routed to the integrated GPU. On lenovo laptops the dGPU is always connected to PEG10 and it is save to disable the PEG slot on dGPU deactivation. Use common gpio.c for southbridge I82801IX. Tested on Lenovo T520 using Nvidia NVS 5200m. Removed Lenovo T430s from the list of supported devices, as the T430s only supports "muxless Optimus". Depends on change id: Iccc6d254bafb927b6470704cec7c9dd7528e2c68 Ibb54c03fd83a529d1ceccfb2c33190e7d42224d8 I8bd981c4696c174152cf41caefa6c083650d283a Iaf0c2f941f2625a5547f9cba79da1b173da6f295 I994114734fa931926c34ed04305cddfbeb429b62 Change-Id: I9b80b31a7749bdf893ed3b772a6505c9f29a56d1 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/12896 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-06-01Revert "mainboard/lenovo/t400: Add initial hybrid graphics support"Patrick Rudolph
This reverts commit 59597ead1f26d4c18997bda81b2ec33e52973b80. Will be replaced by lenovo common hybrid driver. Change-Id: I994114734fa931926c34ed04305cddfbeb429b62 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/12895 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-06-01mainboard/google/reef: Add IFWI region to chromeos.fmdFurquan Shaikh
IFWI region holds different components required for booting including CSE firmware, PMC firmware, CPU microcode as well as the bootblock. Add section for IFWI in chromeos.fmd Change-Id: Ic97980ff222ad7cbd7a2970417b79150256a7a16 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15000 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-31quark: Enable HSUART0 as consoleLee Leahy
The use of HSUART0 on galileo requires early initialization of the I2C GPIO expanders to direct the RXD and TXD signals to DIGITAL 0 and 1 on the expansion connector. TEST=None Change-Id: I11195d79e954c1f6bc91eafe257d7ddc1310b2e7 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15010 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31mainboard/intel/quark: Enable reg_access during romstageLee Leahy
Turn on reg_access during romstage. TEST=Build and run on Galileo Gen2 Change-Id: Iff1616836d6031f43d7741693febefa0bf26b948 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15008 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31mainboard/intel/galileo: Use HSUART1 for consoleLee Leahy
Select HSUART1 for console. TEST=Build and run on Galileo Gen2 Change-Id: I4425af4dc8b3730b3fa2108d6cc2941bc22c2cdb Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15005 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31mainboard/intel/galileo: Split out enabling FSP1_1Lee Leahy
Split out enabling FSP 1.1 support to prepare for enabling FSP 2.0 support. TEST=Build and run on Galileo Gen2. Change-Id: Ic4e814bcf61f9480f98e2d7bc7a1648dec43a07d Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15001 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31soc/intel/quark: Add PCIe reset supportLee Leahy
Migrate PCIe reset from PlatformPciHelperLib in QuarkFspPkg into coreboot. Change-Id: I1c33fa16b0323091e8f9bd503bbfdb8a253a76d4 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14944 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31google/ninja: Upstream AOpen Chromebox CommericalMatt DeVillier
Migrate google/ninja (AOpen Chromebox Commerical) from Chromium tree to upstream, using google/rambi as a reference. original source: branch firmware-ninja-5216.383.B commit 582a393 [Ninja, Sumo: Add SPD source for Hynix H5TC4G63CFR-PBA] TEST=built and booted Linux on ninja with full functionality blobs required for working image: VGA BIOS (vgabios.bin) firmware descriptor (ifd.bin) Intel ME firmware (me.bin) MRC (mrc.elf) external reference code (refcode.elf) Change-Id: I0f1892c24c08fa2d53185b2cf8b6f5a9001b2397 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/14950 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-31mb/gigabyte/ga-g41m-es2l: Update board_info.txt and add item to KconfigDamien Zammit
This adds the website URL to the board info and also enables the realtek nic reset function as per a previous patch. Change-Id: I2cda120c59b55f0dd2ffa78d397b16beb13d6843 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/14954 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31mb/gigabyte/ga-g41m-es2l: Use x4x_late_init()Damien Zammit
This patch adds DMI/EP init to the board and fixes a couple of minor things. Change-Id: I10d0f6ce747b60499680e4dc229b7fcbb16cc039 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/14926 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31mb/gigabyte/ga-g41m-es2l: Fix ACPI IRQ settings for SATADamien Zammit
Previously, due to a bug in devicetree and incorrect IRQ settings in ACPI, SATA controller would not initialize any HDDs in the OS, even though it worked in SeaBIOS. The devicetree setting is not needed because SATA must function in "plain" mode on this board, as "combined" mode does not work at all. Change-Id: I0036c4734de00b84cc3d64f38e4b1fd80fd1a25d Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/14776 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31mainboard/asus/[kgpe-d16|kcma-d8]: Enable secondary serial port headerTimothy Pearson
The ASUS KGPE-D16/KCMA-D8 have an on-board header for a second RS-232 serial port, however it is disabled by default due to the SuperIO default pin mux settings. Enable the secondary serial port early in romstage to allow use during / after initial boot. Change-Id: I5b83659dd8b0d6af559c9ceccee55c4cc2f17165 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14892 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-05-30reef: Remove si-all region from chromeos.fmdFurquan Shaikh
This matches the change in depthcharge fmap.dts to remove si-all region and mark si-desc as ifd. CQ-DEPEND=CL:347986 BUG=chrome-os-partner:53689 BRANCH=None TEST=Compiles successfully Change-Id: Ic7ed94fcdfb9a79bd6ceb960830f67678b0291b6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14990 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-30pcengines/apu1: Rename Kconfig variables for pinmuxKyösti Mälkki
Add APU1 prefix because Kconfig throws errors if we try to define the same variables as choice-entry for APU2 board. Change-Id: Ic071600dd88e391a8a278d63aad13abd01fd3c9d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14988 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-05-27mainboard/google/reef: increase BIOS region sizeAaron Durbin
An updated descriptor expands the BIOS region while descreasing the 'device expansion region' utilized by the CSE. Update the end region marker to reflect this new size as well as the chromeos.fmd file which needs to be adjusted for logical boot parition 2 requirement which resides halfway through the BIOS region. The GBB was moved and shunk to accommodate the change. Change-Id: I7baa5282d7c608af648b5773c4dfa123060a6e45 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14974 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-05-27google/reef: Sync chromeos.fmd with fmap.dts and fix offsetsFurquan Shaikh
CQ-DEPEND=CL:347460 BUG=chrome-os-partner:53689 BRANCH=None TEST="emerge-reef chromeos-bootimage" completes without error Change-Id: Ic954e29628423937604772a8d2d0414954e6ba3e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/347441 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/14975 Tested-by: build bot (Jenkins)
2016-05-27mainboard/google/reef: support verstageAaron Durbin
The chromeos.c suport needs to be linked into verstage so it will link. Change-Id: If85e232a3721443edfbbd278b32f72302f13f3a8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14973 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-26mainboard/intel/amenia: Configure DDI0, DDI1 HPD GPIO lines.Abhay Kumar
1. Configure GPIO_199 and GPIO_200 as NF2 to work as HPD. 2. Make 20k Pullup and remove duplicate code. Change-Id: I8c78d867b03d5f2a6f02165c20777ae25e352ce7 Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Reviewed-on: https://review.coreboot.org/14899 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-26mainboard/intel/amenia: Disable Integrated Sensor HubHannah Williams
Providing an option to enable or disable ISH interface. Leaving it disabled for now. Change-Id: Id4e71d60a6c2da6c6c070d41f66f6c161de38595 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14895 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-25intel/amenia: Extend IFD size by 512 KBBora Guvendik
Increase BIOS region size by 512KB since device extension size is reduced from 1MB to 512KB BUG=chrome-os-partner:52589 TEST=Build Coreboot and boots CQ-DEPEND=CL:*259448,CL:345642,CL:*259445 Change-Id: Ib81b117a3afe730aafa54b4ef31b1e9ab1f67111 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/14929 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-25mainboard/intel/galileo: Enable USB device supportLee Leahy
Turn on the USB device port. TEST=Build and run on Galileo Gen2 Change-Id: Ic1fbb2cd51414ce927f2b408ccd27c7edf978744 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14943 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-24intel/amenia: Configure Trackpad IC_SDA_HOLD timeJagadish Krishnamoorthy
Elan trackpad needs greater sda hold time. Configure IC_SDA_HOLD register to increase the i2c sda hold time by 0.3us. Change-Id: I3d966eed62a059ecb6a0a88e9f4e6b4ba7a925e4 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/14922 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18rockchip: rk3399: enable sdhci clk for emmcShunqian Zheng
If booting from sdcard/usb, kernel can't recognize the /dev/mmcblk0. Before kernel find it's root cause, we add this workaround patch to enable clk for emmc. BRANCH=none BUG=chrome-os-partner:52873 TEST=boot from sdcard and check the /dev/mmcblk0 exists Change-Id: Ie36cc6fdbc24db8c30984c02ccfe2f8aaaf30cd2 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 39b87ec3c73d6f56efc8c3f52b7ed759e548ee85 Original-Change-Id: I88a9cc2e3ea5a56aadfdbd94ef910daaf92a7eb7 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/341632 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14856 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18rockchip: rk3399: configure emmc clkLin Huang
Select aclk_emmc and clk_emmc source from GPLL, and both to 198MHz, that is GPLL(594MHz) divided by 3. BRANCH=none BUG=chrome-os-partner:51537 TEST=boot kevin rev1 to chromeos prompt from both emmc and sdcard TEST=LoadKernel faster, more than twice as I measured manually. Change-Id: I2580c43b8c79049c3fe16bbf60bfa1a8e0559948 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 5fd37b66dcce77354e1cafab0d6e806d832c08d2 Original-Change-Id: Id22815b302af3204e0e5537af99c1577b09b0877 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/339152 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14855 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18ec/google/chromeec/acpi: Add MKBP supportGwendal Grignou
Allow EC to send an interrupt using ACPI SMI when a MKBP event is available. This will be used by the sensor stack. Update all ACPI branch except those without sensors with: for i in $(find . -name ec.h -exec grep -l MAINBOARD_EC_SCI_EVENTS {} \+ | cut -d '/' -f 2 | grep -v -e cyan -e lars); do echo $i cd $i git diff ../lars/ec.h | patch -p 5 cd - done BUG=b:27849483 BRANCH=none TEST=Compile on Samus. Tested in Cyan branch. Change-Id: I4766d1d56c3b075bb2990b6d6f59b28c91415776 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: d3b9f76a26397ff619f630c5e3d043a7be1a5890 Original-Change-Id: I56c46ee17baee109b9b778982ab35542084cbd69 Original-Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/342364 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14854 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-18rk3399: set proper configuration of SDMMC interfaceVadim Bendebury
For proper interface operation the drive strength on all pins is set to 8 mA and all pull ups/pull downs disabled, this matches the current kernel configuration. BRANCH=none BUG=chrome-os-partner:53257 TEST=it is possible to boot Chrome OS on Gru from various micro SD cards which were failing to boot before. Change-Id: Ie43e52a52cd0513d48d0ecc8ac02fbb100baf9a4 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 6bb0549ed728ac3c5faab6cbe16e2487400e67ed Original-Change-Id: I5180537d3ceb74a9a2f7b3982ca94d3e2daf0369 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/344491 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14853 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18gru: set correct gpio for SD card detectVadim Bendebury
The only outlier at this time is Kevin rev 0, treat it specially, the rest of the targets use the same GPIO. BRANCH=none BUG=none TEST=gru still boots off SD card just fine Change-Id: Ic603093a990d27166b16175db3303f155b4775aa Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 5788c5add1d1f803e7b22fb53215b6003ac04d03 Original-Change-Id: Ic5183f08dd1119f9588f243bd9e9c080d84687f9 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/344151 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14851 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18Gru: support 4GB sdram on gruLin Huang
now we use 4GB sdram on gru board, enable it. BRANCH=none BUG=chrome-os-partner:51537 TEST=boot from kevin board Change-Id: Icc483a8ba91c5deea85e6e4009a8a132851b1853 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: efa94aee02bedf51d73c91059b06afcbb1320282 Original-Change-Id: I26f77ff4ad9b2aa35ab5ff50f23984796f4f06bc Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/342585 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14850 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18AGESA vendorcode: Build a common amdlibKyösti Mälkki
Having CFLAGS with -Os disables -falign-function, for unlucky builds this may delay entry to ramstage by 600ms. Build the low-level IO functions aligned with -O2 instead. Change-Id: Ice6781666a0834f1e8e60a0c93048ac8472f27d9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14414 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18mainboard/intel/galileo: Add I2C chip initializationLee Leahy
Add I2C chip initialization for the Galileo boards. TEST=Build and run on Galileo Gen2 Change-Id: Ib5284d5cd7a67de2f3f98940837ceb2aa69af468 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14829 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17mainboard/intel/galileo: Add GPIO initializationLee Leahy
Add Kconfig to configure coreboot for a specific Galileo board. Configure the GPIOs for the specific Galileo board. TEST=Build and run on Galileo Gen2 Change-Id: I992460d506b5543915c27f6a531da4b1a53d6505 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14826 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17intel/sch: Merge northbridge and southbridge in src/socStefan Reinauer
Change-Id: I6ea9b9d2353c0d767c837e6d629b45f23b306f6e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14599 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2016-05-17mainboard/google/reef: add first pass of full pad configurationAaron Durbin
This is an initial stab of configuring the reef pads. Change-Id: I8d8060745af6fbada268c6c6f3492b985ddf9eb8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14831 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@google.com> Tested-by: build bot (Jenkins)
2016-05-13mainboard/google: add reef reference boardAaron Durbin
This adds the initial scaffolding for the reef reference board. One big thing missing is the GPIO configuration. Change-Id: I8e2d275df296bb397bb33dbd0c66fc87c82ff10f Signed-off-by: Aaron Durbni <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14798 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-12soc/intel/apollolake: use common FADT infrastructureAaron Durbin
Instead of having the mainboards duplicate the same boilerplate code utilize the common FADT infrastructure to reduce duplication. Change-Id: If824619fd619433974e588050a933d2c19b97ec8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14779 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-12intel/amenia: Enable touchscreen in ACPIFreddy Paul
Add support for Elan touchscreen on I2C3 for amenia BUG=None TEST=Boot to Chromium OS and verify if touchscreen is working. Change-Id: Ic75bef0e5878bd5b8c0d727400679663d9f591e3 Signed-off-by: Freddy Paul <freddy.paul@intel.com> Reviewed-on: https://review.coreboot.org/14768 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-11lib: remove FLASHMAP_OFFSET config variableAaron Durbin
The FLASHMAP_OFFSET config variable is used in lib/fmap.c, however the fmdtool creates a fmap_config.h with a FMAP_OFFSET #define. Those 2 values are not consistent. Therefore, remove the Kconfig variable and defer to the #define generated by fmdtool. Change-Id: Ib4ecbc429e142b3e250106eea59fea1caa222917 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14765 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-10google/gale: use if (IS_ENABLED()) over #ifdefPatrick Georgi
Change-Id: I9047251608fbb92180f2e92d19fd128c5f1ef399 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14754 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-10google/gale: mark RW_LEGACY to carry CBFSPatrick Georgi
Change-Id: I9422d6ca2601dcc6e3d7c4a2c413c32015c10e00 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14753 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-10soc/qualcomm/ipq40xx: Enable crashdump handlingVaradarajan Narayanan
Clear the crash dump cookie set by SBL to indicate that it is a normal reset. Inform DDR image of the entrypoint for SDI image to be preserved in OCIMEM which will be needed during watchdog resets. BUG=chrome-os-partner:49249 TEST=DDR image is able to fetch the entry point address BRANCH=none Change-Id: I3e6e4a108585bb257e3ad02956c420acbcb2554e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bd726256a5ae89672810b57e1d2a7a9287f60627 Original-Change-Id: Id6e09516209f47c3ea8fa3d8d90440789b395660 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333321 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14679 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-10soc/qualcomm/ipq40xx: Add support for BLSP QUP I2CVaradarajan Narayanan
Able to talk to the TPM device and the commands seem to succeed. BUG=chrome-os-partner:49249 chrome-os-partner:49250 TEST=All commands to the TPM succeed BRANCH=none Original-Commit-Id: c13900108f524c8422c38dee88469c8bfe24d0bd Original-Change-Id: Ie8c3c1ab1290cd8d7e6ddd1ae22f765c7be81019 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333314 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> squashed: soc/qualcomm/ipq40xx: Add support for BLSP QUP SPI - Enable BLSP SPI driver for ipq40xx - supports only FIFO mode BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: 0714025975854dd048d35fe602824ead4c7d94e9 Original-Change-Id: If809b0fdf7d6c9405db6fd3747a3774c00ea9870 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333303 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ia518af5bfc782b08a0883ac93224d476d07e2426 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14677 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-10google/gale: Remove some unwanted codeVaradarajan Narayanan
BUG=chrome-os-partner:49249 TEST=Compiles and boots BRANCH=none Original-Commit-Id: 96a125f99af3eaa8931563fa74ccef8dd997f3ca Original-Change-Id: Iebfe7429c400e7119510a51c3124d432f00af76d Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333319 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> squashed: soc/qualcomm/ipq40xx: Add function to reset TPM BUG=chrome-os-partner:49249 TEST=Able to read TPM registers BRANCH=none Original-Commit-Id: 9df3e9dfe61382143394a58a3a927c05a875b377 Original-Change-Id: I38732acc4418c94b88a430ba697db4e3b145c341 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333317 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ifc8df3b7e231eef944efec3a6f973b402c11bcaf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14674 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-10google/gale: Enable WinBond SPI flash supportVaradarajan Narayanan
BUG=chrome-os-partner:49249 TEST=Able to read content from SPI NOR, with boards having WinBond SPI Flash BRANCH=none Change-Id: I104a750aa6545264003cd785c347cb9354e59b5c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b933c7eeb133201877596c39cf4b3c263aca5498 Original-Change-Id: Ida767dab3abe72def2388e5eeb41eeb575205528 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/339872 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14672 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-10soc/qualcomm/ipq40xx: Map OCIMEMVaradarajan Narayanan
DDR binary runs from here BUG=chrome-os-partner:49249 TEST=Boots and DDR seems to be usable BRANCH=none Change-Id: I6111dddcabf05e5cb84ee9ebcc1803addb1e91cf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7baf2079845964a150f51d558b396a1a9b0dc0a3 Original-Change-Id: I1d7230b229db3abfb73e6d8f9ca085650e6abec8 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333313 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14671 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-10google/gale: Remove NAND initVaradarajan Narayanan
This is stale code from ipq806x, n/a for ipq40xx. Hence removing it. BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Change-Id: I2ac73677f77d4bfbc70f56c73a661cc2c22dd384 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2f9796588648bc477f118282aad89037f0577f23 Original-Change-Id: I8bcf928ee23ac24a21b0e633e207354ea9fa0511 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333299 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14664 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-10google/gale: Implement resetVaradarajan Narayanan
Implement reset using PSHOLD and remove watchdog based reset not needed for ipx40xx. BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Change-Id: Ic2fa0e7676604f36a99750b4bda53195199ebc69 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 65c8b9dd633f0d402cad7d609563c8aac9bf5115 Original-Change-Id: I8f0ea3c1b71e86a7ca733965ecbec6954a52f6e3 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333298 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14750 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-10google/gale: Implement resetVaradarajan Narayanan
Implement reset using PSHOLD and remove watchdog based reset not needed for ipx40xx. BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Change-Id: Ibd3f9958682ed2e85e778976df3a8e124a7441fd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 65c8b9dd633f0d402cad7d609563c8aac9bf5115 Original-Change-Id: I8f0ea3c1b71e86a7ca733965ecbec6954a52f6e3 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333298 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14663 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-10google/gale: Enable Giga Device SPI flash supportVaradarajan Narayanan
BUG=chrome-os-partner:49249 TEST=Able to read content from SPI NOR, with boards having Giga Device SPI Flash BRANCH=none Change-Id: I67dc981a8c0270d55b01bdc4506139cccd8e90a7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 417701816e8a298ba999d2c2d0d058cf7b54fb6f Original-Change-Id: Id09ef68b13c53a2ab44f77c12dad39b505c81071 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333320 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14661 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-10soc/qualcomm/ipq40xx: Return NULL for cbmem_top if DRAM is not initializedVaradarajan Narayanan
DRAM initialization on gale requires ipq blobs to be loaded from cbfs. vboot_locator first checks cbmem_find to see if cbmem is initialized and contains selected region info, else it falls back to vboot work buffer. Since cbmem_find calls into cbmem_top to identify the location of cbmem area, board/chipset is expected to return NULL until the backing store is ready, which in this case until DRAM is initialized in romstage, return NULL for cbmem_top. BUG=chrome-os-partner:49249 TEST=Able to compile and boot to depthcharge. Doesn't crash in imd_handle_init_partial_recovery BRANCH=none Change-Id: Iaac24252ee4fb9f59d767730bf9dd68baa42a68f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4849c15dee2d3782ede4ee4157e432bd4d5602f0 Original-Change-Id: I3722b7ab5a6585a250138c828eb3d7919b0c1178 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/335425 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14660 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-10google/gale: set the correct GPIOs for recovery and dev.Kan Yan
BUG=chrome-os-partner:49249 TEST=Recovery swich functions correctly. BRANCH=none Change-Id: I88bb973a82133d8bab6b79fd49c8052f64937473 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c8d319f65ee75e3c01e63c44249c7c7871a77518 Original-Change-Id: I2f62f2549c519f52c12c351dcb881a088671934a Original-Signed-off-by: Kan Yan <kyan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/334414 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14658 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-10soc/qualcomm/ipq40xx: Update memory map to align to ipq40xxVaradarajan Narayanan
Update the memory to map to align with the internal memory region map of IPQ40XX BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: e33712a729ef9831508c2e9aae81d0b32495b681 Original-Change-Id: Iba1c5281a2fbda4ab96126676b901ba71f6b28e0 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333295 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> squashed: soc/qualcomm/ipq40xx: Update DRAM address ranges BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: 9150c125cb82f8dccb1347d898106703d85a5192 Original-Change-Id: Ic48d3e3f46a7c13a009a5cbed20984bd253eb85b Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333296 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Change-Id: Iea40484751a1c0439ed511319ef09a0254eba757 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14654 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-10google/gale: Initial commit for Gale board supportVaradarajan Narayanan
Copy 'storm' files as a template BUG=chrome-os-partner:49249 TEST=None. Initial code. Not sure if it will even compile BRANCH=none Original-Commit-Id: 4bfabf22cb33ac2aacff0ebeed54655664505148 Original-Change-Id: I94e361911b89c5159b99f3d00efbcda94f763e71 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Signed-off-by: Kan Yan <kyan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/333177 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> squashed: google/gale: Remove unwanted config option 2016.02 doesn't seem to like CONSOLE_CBMEM_DUMP_TO_UART BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: 44b91a8f83515936156206f9f273e0e5c62c3f17 Original-Change-Id: I9294ff602a05e4c9573fee3b9b51f9cc5305e192 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333302 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> google/gale: Update ipq806x/storm references Since the files were taken from ipq806x/storm as template. Update those references to reflect ipq40xx/gale. BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: fa5962b757dbb6cc9e1e6d1e33e1e09ec6cb4cd2 Original-Change-Id: Ia330367a0547ac4306ef2514dc1305e2d65f80e4 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333292 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> google/gale: Update fill_lb_gpios for new scheme This updates fill_lb_gpios to follow the new scheme introduced in CL:337176. BUG=none BRANCH=none TEST=chromeos.c compiles successfully for gale Original-Commit-Id: 635d7fd71d91552bd7470faeb5637ba1a727f940 Original-Change-Id: I6f98325918b350645b9c19b71125bc12a54953ab Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/338651 google/gale: Add '.fmd' file BUG=chrome-os-partner:49249 TEST=None. Initial code. Not sure if it will even compile BRANCH=none Original-Commit-Id: 474de31f7ed0adbe54251ca363e685019091b4e7 Original-Change-Id: I4019b110af676090e8751b315dadc5b601a56178 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333291 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Change-Id: Iad8e010371f3b9b92ab26eee4ba35c4f16d3732c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14642 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-10siemens/mc_tcu3: Don't try to init unsupported panel typeWerner Zeh
The LCD panel type is read using 4 GPIOs. Of these 16 possible combinations only 5 are supported right now. If the GPIO setting encodes an unsupported panel type, there will be no matching hwinfo.hex in cbfs. Therefore it makes no sense to try to initialize the DisplayPort-2-LVDS converter. Leave the function instead in this case. Change-Id: If8c67a3f5be762758d516c4939dd1de4ff1c8ba5 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/14743 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2016-05-10AGESA boards: Relocate platform memory configKyösti Mälkki
File buildOpts.c is a can of worms, pull platform memory configuration in to OemCustomize.c. This array should be assigned at runtime instead of linking a modified defaults table. Change-Id: I73d9d3fbc165e6c10472e105576d7c40820eaa6a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14528 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-10AGESA boards: Rename files containing OEM configurationKyösti Mälkki
There are other things besides PCIe port configuration that require board specific hooks. Change-Id: I0923651487b9ed5f6f7569ce08e02d993fa5f976 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14527 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09mainboard/asus/[kgpe-di6|kcma-d8]: Fix board ROM informationTimothy Pearson
The board information file incorrectly listed an LPC ROM. Fix the information file to show the correct SPI ROM. This patch changes a human-readable file only, and does not alter functionality. Change-Id: Ib5c1789fa636354f2b6c92faf44b45b32d1ec544 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14742 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-09google/gru: enable pp1500 and pp3000 rails as soon as possibleVadim Bendebury
The idea is that they stay low unless we know that we booted from SPI flash. As this code runs in SPI flash - it is ok to turn these rails on as soon as possible, and pp3000 rail it is essential for UART to work. Kevin rev1 and Gru designs are going to be using these pins to control these rails. Kevin rev1 had those GPIO pins routed to two chip enable signals, it is save to assert them high. BRANCH=none BUG=chrome-os-partner:51537 TEST=kevin rev0 still boots (which does not prove much) TEST=run coreboot on kevin rev1 to kernel Change-Id: I5f3eb4cf5d6f04a0253574dd8b5c039eab0bae1a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 987042246672e9391087dbd5060785a379dde131 Original-Change-Id: I31bb03334ad9e3aa57db726fb43dec85014a3f05 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/341543 Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-on: https://review.coreboot.org/14729 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09google/gru: kevin: use board version specific SD detect GPIO pinVadim Bendebury
This change reflects Kevin schematics differences, Gru will have to be addressed separately. BRANCH=None BUG=None TEST=the code still works fine on Kevin proto 1. Change-Id: Iecae0e82e6bd4d185b49587b6053dcef8ad2162d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e821bbebe902a293b1e78cdd868f6bf3548ddd30 Original-Change-Id: Icd606285aeca1e19189f5e3d24c09b376942708b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/340429 Original-Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: https://review.coreboot.org/14728 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09google/gru: select 1.8V as gpio2ab io domainLin Huang
On kevin board, both the gpio2ab's io domain APIO2_VDDPST and APIO2_VDD are 1.8V. So gpio2ab can only output 1.8V. BRANCH=none BUG=chrome-os-partner:52510 TEST=Apply this patch, CPU1_SDIO_PWREN(GPIO2_A2) can output 1.8V Change-Id: Iefe58cf5ad83a8e79916ad177d148c1036283668 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9c4afee265f3f31c1defee08cb89ab3e45ff8d1a Original-Change-Id: I0216c8efb7ef9256b878adeeee0a52335bf69f93 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/337194 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14726 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09google/gru: add board nameVadim Bendebury
Gru is the common name of a set of coreboot boards, each of them has the config option BOARD_GOOGLE_GRU enabled. Now we need to add the actual board called Gru to the set. Let's rename the common config option to BOARD_GOOGLE_GRU_COMMON and use BOARD_GOOGLE_GRU for the actual board. BRANCH=none BUG=none TEST=with corresponding depthcharge and configuration space changes it is possible to build the Gru board which boots the kernel using the proper compatibility string of google,gru-rev0 Change-Id: I363d4b690b7549f50ed75d77b56e6a1e1d17b60f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 327ecc0de20ac0b93ec3cd28ef398393d4ea7c42 Original-Change-Id: Ia43278225c2d32d2af37193a77ea792551c9f8d9 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/340793 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14724 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09google/gru: Determine Board ID based on the input voltage of ADC1Vadim Bendebury
The Board ID on the Gru family of boards is determined by reading the voltage from a resistor divider, each hardware revision is supposed to have a unique resistor ratio, which allows to distinctly tell between different Board ID. While the long time approach to mapping resistor ratios (and voltages) into Board ID remains under discussion, we know for sure the values for Proto 1 and Proto 2. Let's just use them for now. Since Board ID can be queried multiple times during boot, ideally it should be read once and placed in the coreboot table to be available to all coreboot stages. For now we just cache it so that at least during the same stage the ADC has to run only once. BRANCH=None BUG=chrome-os-partner:51537 TEST=verified that the voltage reading on Proto 1 is as expected, and Board ID 0 is reported. Change-Id: I94bc7fc235dae4155feb6ca35b5ef0ab20c3ec9c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bb4064d0af8174b6ae247cdad9378b7f4e5f22ba Original-Change-Id: I105ea97f8862b5707b582904c6f2e3e9406a0f07 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/340428 Original-Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: https://review.coreboot.org/14722 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09google/veyron_mickey: Increase RO CBFS size by 512 KbDavid Hendricks
This change increases the size of RO CBFS by 512 Kb to accommodate new images added to the INSERT screen. (This does the same thing as Daisuke's CL:338095, but for Mickey) BUG=chromium:604412 BRANCH=none CQ-DEPEND=CL:339495,CL:339511 TEST=emerge-veyron_mickey chromeos-bootimage Change-Id: Ib58247b2c89e436c6013f3ad59ad1cb80ba14964 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 897499bea5bd4003466ca7ebabff597e87da2e45 Original-Change-Id: I2cee79b2476fcb5bfb91bf9779f1fe11b4361612 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/339542 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/14721 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09google/gru: power up SD cardVadim Bendebury
Make sure SD card is powered up properly. Please refer to TRM V0.3 Part1 Page 324 for sdmmc pinmux. BRANCH=none BUG=chrome-os-partner:51537 TEST=With other patches, boot into chromeos prompt Change-Id: Ib53b05c1fce851ca7cbcc2207fce2dce3b1bfe9a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d37e688a458749e331a50c2ebf2018cba6629823 Original-Change-Id: I9f67c0bc16ddefa5ebe52a10c6d9e54194828a89 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/337192 Reviewed-on: https://review.coreboot.org/14718 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: add sdram driverLin Huang
Add the sdram driver for rk3399. With this patch we can boot into depthcharge. This patch also include a config file for lpddr3-hynix-4GB that generated bases on its datasheet. Please refer to TRM V0.3 Part1 Chapter 9 for DMC. BRANCH=none BUG=chrome-os-partner:51537 TEST=boot to depthcharge on kevin Change-Id: I2afcaa3b68dbad77a5fe677b835289b675ed2bef Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5d777e29942057fb7237eefa34051d1f54b19405 Original-Change-Id: Ifa1fe98a7058869518757d50678a64620610d91d Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/332562 Reviewed-on: https://review.coreboot.org/14716 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: add spi clock driverShunqian Zheng
This patch implements spi clock driver and initialize SPI flash rom for the baseboard gru. There are 6 on-chip SPI controllers inside RK3399. For SPI3, it's source clk from ppll, while the others from gpll. Please refer to CRU session of TRM for detail. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I597ae2cc8ba1bfaefdfbf6116027d009daa8e049 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4c6a9b0aedd427727ed4f4a821c5c54fb3a174b9 Original-Change-Id: I68ad859bf4fc5dacaaee5a2cd33418c729cf39b8 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/338946 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14710 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09google/gru: enable uart2 if configuredShunqian Zheng
This patch select gpio pins for UART2 which is the default debug port of rk3399. Please refer to TRM V0.3 Part1 Page 325,395 for GRF details. BRANCH=none BUG=chrome-os-partner:51537 TEST=check logs from console manually Change-Id: I91eeadd543e7e895c3972d8dd7a2195c9d78968b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0c51955e18d4ff9cd3208697666af4fa77046e0f Original-Change-Id: I960178628f4020a59d100f2f0b2a6be487892549 Original-Signed-off-by: hunag lin <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/338945 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14709 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09google/veyron_romy: Increase RO CBFS size by 512 KbDaisuke Nojiri
This change increases the size of RO CBFS by 512 Kb to accommodate new images added to the INSERT screen. BUG=chromium:602147 BRANCH=tot TEST=emerge-veyron_romy chromeos-bootimage CQ-DEPEND=CL:338152,CL:338027 Change-Id: I37cd0a9486f46d02cbc64af60336290fbbf486a8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4692cad8fc939202af2e3de709c2835a854e64b2 Original-Change-Id: I2f117247b2971a6f5576f60cdd53624ad6867e78 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/338095 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14702 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09google/oak: Add Samsung K4E6E304EB 4G LPDDR3 SDRAM for elm-rev1 SKU2PH Hsu
BUG=none BRANCH=none TEST=emerge-elm coreboot Change-Id: Ib40076f2bb1516fe222e52e18592c15073c9d288 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 84d188543a9e949f7bf792ba704263a0bf97aa51 Original-Change-Id: I43ea6f07f5e337ca3bc5c5c4b3d56c89e5e0ca98 Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/338212 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14695 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09google/oak: elm: Do not control SPI_LEVEL_ENABLE after elm-rev1Yidi Lin
SPI level shifter is controlled by SRCLKENA0 after elm-rev1. We don't need to configure it in the bootloader. BUG=chrome-os-partner:51725 TEST=emerge-elm coreboot Change-Id: I01ec00965b87ae370b72d3c0521fb37268714cf8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3234065e33c46bc2d67a96939422d318919d5e7a Original-Change-Id: Iafed0cd7562eb5921af6b17f73a067d469143e02 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/337421 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14694 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09google/oak: Configure MAINBOARD_PART_NUMBER by the board nameYidi Lin
BRANCH=none BUG=none TEST=check CONFIG_MAINBOARD_PART_NUMBER value in the coreboot.config Change-Id: Iefae44f4cd16d0e749f5b88d80ef6e5c23498c6d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 99b26f5a68054619c519c945172e56c10f353558 Original-Change-Id: I51c47d114049caf04ccb491096b39696e6af2ab3 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/339800 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14693 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09google/oak: elm: Update the differences between oak-rev6 and elm-rev0Yidi Lin
- Remove the deprecated revison settings. - Change LID pin to SPI_CK. - Add i2c bus number and i2c slave address for elm. - Skip the pin configurations(ALC5514 and USB OC pins) belonging to Oak. - Add Hynix 4GB DRAM config BRANCH=none BUG=chrome-os-partner:51725 TEST=boot to kernel on elm-rev0 Change-Id: Ifaedd115c84d095ee289b576ff76af6b0aa3e545 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2ed4543cdc7e84a0463b73dda96027270ec30272 Original-Change-Id: Id957374d7a67b8c72df1d07a6cecc1064d4e0356 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332733 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14692 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09google/oak: Add derivative board ElmJulius Werner
This patch adds a new mainboard Google/Elm as a derivative of Google/Oak, using the same code sharing technique for derivative boards that was pioneered with Google/Veyron*. For now, there are no firmware-relevant fundamental differences between the two boards. In addition, introduce a board-specific Kconfig for the "board ID adjustment" to represent the fact that the Elm board ID space mirrors the Oak board ID space with an offset of 6, meaning Elm rev0 is equivalent to Oak rev6, and future board changes will be made on both boards to maintain this stride (at least virtually... not all of those revisions will necessarily get built). This should make it much easier to keep the code that handles revision differences somewhat clean. (That's the theory, anyway... whether it will work out remains to be seen.) BRANCH=None BUG=None TEST=Booted Elm image with hardcoded board ID 0 on Oak rev6. Change-Id: If540aea862b746cf4986a74482ae1764c104fb73 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 53cd85c94945ab0bf14cb88a98e66723fc4483de Original-Change-Id: Ib05fc81dc4f4308d99e34fce74c6db8b323785da Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/332276 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14691 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09google/oak: configure displayJitao Shi
BRANCH=none BUG=chrome-os-partner:43706 TEST=saw bootloader screen on rev4 and rev5 Change-Id: I844fed6f63467ad04d17115934a1e4724cc0b671 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2e9d57a42402631923c96e70bc2eff5c135de2fc Original-Change-Id: I748b0eac9a0aab1d38d5d44a1a50dc33d5375379 Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/331813 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/14690 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-03 19:45:51 +0000