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2009-11-25Trivial style changes, replace a few C++ type comments, and some code reusePeter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4956 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-25This patch is buzzer of TechNexion TIM-5690.Libra Li
I forgot to svn add the speaker.c and speaker.h. Signed-off-by: Libra Li <libra.li@technexion.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4955 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-25This patch is buzzer of TechNexion TIM-5690.Libra Li
Change EARLY_STAGE into __PRE_RAM__. Signed-off-by: Libra Li <libra.li@technexion.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-18This is a patch to control the DIP switch and digital I/O.Libra Li
Signed-off-by: Libra Li <libra.li@technexion.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4948 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-12Add CONFIG_WARNINGS_ARE_ERRORS and set it for qemu.Myles Watson
Remove all remaining warnings from qemu. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4939 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-09These are post codes for TIM-5690 LED debug message.Libra Li
Signed-off-by: Libra Li <libra.li@technexion.com> Added object reference to Config.lb, too and Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4928 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-06Remove drivers/pci/onboard. The only purpose was for option ROMs, which areMyles Watson
now handled more generically using CBFS. Simplify the option ROM code in device/pci_rom.c, since there are only two ways to get a ROM address now (CBFS and the device) and add an exception for qemu. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-06Remove some white space and comment differences from devicetree.cb and Config.lbMyles Watson
files. These boards have non-trivial differences: gigabyte/m57sli kontron/986lcd-m dell/s1850 via/epia-m700 Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4924 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-06Drop all pre-CBFS rom_address entries in Config.lb/devicetree.cb.Uwe Hermann
Since we have CBFS setting rom_address in board files is no longer necessary. Also, drop vga_rom_address from RS690 completely, it was never used in the code. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-06Split the two usages of __ROMCC__:Myles Watson
__ROMCC__ now means "Don't use prototypes, since romcc doesn't support them." __PRE_RAM__ means "Use simpler versions of functions, and no device tree." There are probably some places where both are tested, but only one is needed. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4921 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-06Remove hard coded bus numbers from arima/hdama mptable code and fix warnings.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4920 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-05fix length field in dmi tables. Newer DMI versions through errorsStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-31Set SB_HT_CHAIN_ON_BUS0 correctly for arima/hdama. Trivial. Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4903 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-30Fix, um... a typo.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4892 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-30Allow per-northbridge and per-board VGA BIOS file name and PCI ID defaults.Uwe Hermann
Of course, the user can still override those defaults, if needed. Add defaults for VIA pc2500e, Kontron 986LCD-M/mITX, MSI MS-6178. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-28Fix some builds with Kconfig.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4883 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-28Make d945gclf build.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4882 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-28Add some missing license headers, consistency fixes for others (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4881 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-28preliminary Intel D945GCLF Atom+i945 support.Stefan Reinauer
ram init fails, as the i945 driver currently only supports the mobile version of the chipset.. Not sure how much sense it makes to check this in, but since it's a nice and cheap board, maybe someone wants to work on this. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-27Update arima/hdama to detect how many nodes there are. Compare to tyan/s2892.Myles Watson
Fixes booting for Hugh. Various white space fixes as well. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4870 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26cp src/mainboard/tyan/Makefile.k8_CAR.inc to src/mainboard/Makefile.k8_ck804.incMyles Watson
Make more boards use both of them. Trivial. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26Move src/mainboard/tyan/Makefile.s289x.inc to src/mainboard/Makefile.k8_CAR.inc.Myles Watson
Trivial. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4867 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26Add kconfig menus for most chipset VIDEO_MB values.Uwe Hermann
VIDEO_MB is a variable that defines how many MB of RAM will be used for onboard graphics frame buffer. It's northbridge-dependent which values for CONFIG_MB are valid (but not board-dependent). This patch adds choices for menuconfig to select the VIDEO_MB value for: - Intel 82810 - Intel 82830 - VIA CN400 - VIA CN700 Note: CN400 and CN700 are based on the CX700 datasheet, not sure if they're correct. If somebody has CN400 and CN700 datasheets, please verify. We drop all per-board VIDEO_MB variables in per-board Kconfig files as there's a northbridge-specific option/default now (plus the user can override the value if needed in menuconfig). As CONFIG_MB is chipset-specific but not board-specific (and never was), filter it in util/compareboard/compareboard, we don't need to match those values. Finally, put "CPU", "Northbridge", "Southbridge", "Super I/O", and "Devices" sections into the "Chipset" menu, where NB-specific options will appear if you select a board using a certain NB, SB-specific options would appear in the "Southbridge" section etc. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26Fix iei/pcisa-lx-800-r10. Trivial.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4865 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26Kontron 986LCD-M updateStefan Reinauer
- run ACPI code through preprocessor so we get the same values as the C code - fix PCIe x16 slot - fix ICH7 Azalia/HDA driver - SMI/GNVS update security fix (only allow struct pointer update once) - ACPI updates - IDE driver fixes - add cmos options for disabling onboard ethernet and controlling system fan Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4861 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26Use Intel Core code for eagleheights CAR init, not Intel Core 2, asStefan Reinauer
any of the CPUs might be used. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4858 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26Define some variables that were not defined. There are a couple left.Myles Watson
Do kbuildall then grep not.defined kbuildall.results/* The interesting ones were GENERATE_* I had to put them in twice to make it work correctly: once outside the menu setting the defaults, and once inside the menu. Now they show up when they should, and are always defined Define HAVE_INIT_TIMER to only exclude the three boards that define it to be 0 in newconfig. Define MEM_TRAIN_SEQ to be an integer and set it correctly. Remove CAR_FAM10 and just depend on NORTHBRIDGE_AMD_AMDFAM10 MOVNTI is a performance enhancement, and should default to 0 so it doesn't break boards that forget to define it. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4856 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24Fix intel/xe7501devkit build, missing "uses" clause.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4851 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24Major cleanups of the hard_reset() code and config in coreboot.- supermicro/x6dhe_g/auto.c
- Drop unused "#object reset.o" entries. - Use CONFIG_HAVE_HARD_RESET for all "object reset.o" entries. - Drop dead/commented code, i.e. useless hard_reset() from: - supermicro/x6dhe_g/auto.c - supermicro/x6dhe_g2/auto.c - supermicro/x6dhe_g2/auto.updated.c - supermicro/x6dhr_ig/auto.c - supermicro/x6dhr_ig2/auto.c - digitallogic/msm586seg/auto.c - dell/s1850/auto.c - Add "obj-$(CONFIG_HAVE_HARD_RESET) += reset.o" to kconfig files of boards that actually have a reset.c file. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4849 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24move all register fram definitions to arch/register.hStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4832 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-23Drop dead K8_SCAN_PCI_BUS code. It's a bad idea to scan the PCI busses beforeMyles Watson
RAM is initialized, and no one does it. Trivial. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-23drop a lot of dead code, including an old winbond southbridge from our removedStefan Reinauer
ppc port, some ambiguous use of CONFIG_IDE and an unused ide driver (we dropped the filesystems already to be used with it) (somewhat trivial) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4828 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-22The LAN chip-set on the Technexion TIM-5690 is enabled by hardware andLibra Li
does not need any handling in software. Signed-off-by: Libra Li <libra.li@technexion.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4822 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-21Add CONFIG_VGA_ROM_RUN to HP e-Vectra P2706T to make VGA init work.Uwe Hermann
Also add pci_rom entries (commented) to targets/hp/e_vectra_p2706t/Config.lb for the same reason. They have to be uncommented to be used. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4821 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-20Add initial support for the HP e-Vectra P2706T.Uwe Hermann
Boot-tested by Paweł Stawicki <stawel@gmail.com>. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Paweł Stawicki <stawel@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4820 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-20Minimize differences between newconfig and Kconfig for arima/hdama.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4819 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-20Remove CONFIG_CPU_AMD_FAM10 & CONFIG_CPU_AMDK8 from mainboards. They should beMyles Watson
selected in sockets, and they aren't used yet. Add a couple of variables to src/Kconfig for lack of a better place so that their selects work. Add select statements according to newconfig for some variables that were defined but never selected in mainboard configs. Fix #if CONFIG_VGA==1 -> #if CONFIG_VGA. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4816 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-20Fix all board names in Kconfig as per wiki / vendor website.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4815 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-19Fix builds of amd/db800 and digitallogic/msm800sev with smaller bootblocks.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4811 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-19Unselect AP_CODE_IN_CAR in tyan/s289x. Trivial.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4810 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-19Clean up some #ifdef CONFIG_*Myles Watson
Change HAVE_FAN_CTL to be specific to the SuperIO that supports it. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-18Drop a duplicated implementation of failover.c.Uwe Hermann
Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4807 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-18Simplify Kconfig files by using "select" where possible (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4806 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17Move files from src/cpu/x86/{fpu,mmx,sse}/ to x86/Peter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4803 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17Remove CONFIG_ from #defines that aren't config variables. Trivial.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4802 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16This is a snapshot as the availability of the systems for this Ronald G. Minnich
project is now uncertain, and I can't invest the remaining time needed to get it done. Status is that memory is still not quite configured correctly. It is close but here are DRAM Row Boundary registers. Here is coreboot 60: 10 10 20 20 20 20 20 20 00 00 00 00 00 00 00 00 This is close. But: 60: 10 10 10 10 20 20 30 30 00 00 00 00 00 00 00 00 is the real hardware. So we are somehow missing those last slots. I think it's because the SPD connections and the chip connections differ, some dumping of RAM registers differ. But it's very close. This is under serialice. Once we get to this point we get stuck here: Copying coreboot to RAM. Copying coreboot to RAM. Copying coreboot to RAM. Forever. Here is the total config for 0:0.0 from coreboot: PCI: 00:00.00 00: 86 80 90 35 06 00 90 00 0c 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 40: 09 00 05 41 10 00 00 00 00 00 00 00 00 00 00 00 50: 0c 60 2a 00 00 00 00 00 00 30 33 33 33 33 33 33 60: 10 10 20 20 20 20 20 20 00 00 00 00 00 00 00 00 70: 0a 0a 00 00 00 00 00 00 67 11 5e 55 1e 02 20 2c 80: 41 28 21 00 00 00 00 00 80 01 00 f0 00 00 00 00 90: 00 00 00 00 00 a1 04 39 aa aa 0c 30 5f 08 02 07 a0: 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 b0: 32 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 44 c0 50 11 00 c0 ff 03 00 00 df 03 20 00 00 e0 d0: 02 28 00 0e 07 00 00 00 00 00 93 b5 00 00 00 00 e0: 00 00 00 00 00 00 00 00 36 3c 00 00 00 00 00 00 f0: 00 00 00 00 3a 01 42 00 80 0f 0c 00 00 00 00 00 And from factory: 00:00.0 Host bridge: Intel Corporation E7520 Memory Controller Hub (rev 09) 00: 86 80 90 35 46 01 90 00 09 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 6c 01 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 40: 09 00 05 41 10 00 00 00 00 00 00 00 00 00 00 00 50: 0c 20 6a 00 00 00 00 00 00 10 11 11 01 00 00 10 60: 10 10 10 10 20 20 30 30 00 00 00 00 00 00 00 00 70: 0a 00 0a 0a 00 00 00 00 44 11 5e 55 1e 02 20 2c 80: 41 28 41 00 00 00 00 00 80 01 00 f0 88 00 00 00 90: 00 00 00 00 00 aa 04 39 aa aa 0c 30 75 08 12 07 a0: 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 b0: cc 00 99 55 00 00 00 00 00 00 00 00 00 00 00 00 c0: 44 c0 50 33 00 e0 60 00 67 00 28 00 30 00 00 e0 d0: 02 28 00 0e 03 00 00 00 00 00 93 b5 00 00 00 00 e0: 00 00 00 00 00 00 00 00 3a 3c 00 00 00 00 00 00 f0: 00 00 00 00 10 01 02 00 80 0f 0c 00 00 00 00 00 I want to commit this because even if I get no further, someone else might. Note that for serialice you need the following temporary patch as well: Index: src/superio/nsc/pc8374/pc8374_early_init.c =================================================================== --- src/superio/nsc/pc8374/pc8374_early_init.c (revision 4791) +++ src/superio/nsc/pc8374/pc8374_early_init.c (working copy) @@ -29,7 +29,8 @@ static void pc8374_enable_dev(device_t dev, unsigned iobase) { pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); +/* don't disable for now, it kills serialice */ + pnp_set_enable(dev, 1); Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4796 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16Fix AP_CODE_IN_CAR (only selected for two boards), STACK_SIZE, and HEAP_SIZE.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4793 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16Drop enable_mmx.inc. It reads (only) "Enabling mmx registers is a noop"Peter Stuge
abuild tested Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4791 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16Set default ROM sizes per-board to match the ROM chip that cameUwe Hermann
with the respective board. Of course, the user can still override the size in menuconfig. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4790 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16Drop unused and useless CONFIG_MAX_PCI_BUSES.Uwe Hermann
It was added by rsmith in r2273 on 20060424, when pci_locate_device() in src/arch/i386/include/arch/romcc_io.h in fact scanned all busses: - for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { + for(; dev <= PCI_DEV(CONFIG_MAX_PCI_BUSES, 31, 7); dev += PCI_DEV(0,0,1)) { Today this looks like: for(; dev <= PCI_DEV(255|(((1<<CONFIG_PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) { and CONFIG_MAX_PCI_BUSES is never used anywhere. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4789 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16Change CONFIG_LB_MEM_TOPK to CONFIG_RAMTOP to match CONFIG_RAMBASE.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4788 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16Fix IRQ9 and allow ACPI without an MP table for Tyan s289x.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4787 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16Fix kconfig setup for the VIA pc2500e.Uwe Hermann
Add/drop Kconfig variables as needed. In Makefile.inc just include Makefile.romccboard.inc with -mcpu=c3. Build- and runtime-tested on hardware. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16Add CONFIG_VGA_ROM_RUN to dbm690t and pistachio, otherwise theZheng Bao
VGA ROM can not run. After make, run > ./cbfs/cbfstool ./coreboot.rom add ../vga_bios.rom pci1002,791f.rom optionrom to make the final image with vga bios. The macro vga_rom_address is out-of-date when CBFS starts play its role. it also should be eliminated from rs690/chip.h as below. But it will cause building error on other board, which I cant make test on. ## Index: src/southbridge/amd/rs690/chip.h ## =================================================================== ## --- src/southbridge/amd/rs690/chip.h (revision 4782) ## +++ src/southbridge/amd/rs690/chip.h (working copy) ## @@ -23,7 +23,6 @@ ## /* Member variables are defined in Config.lb. */ ## struct southbridge_amd_rs690_config ## { ## - u32 vga_rom_address; /* The location that the VGA rom has been appened. */ ## u8 gpp_configuration; /* The configuration of General Purpose Port, A/B/C/D/E. */ ## u8 port_enable; /* Which port is enabled? GFX(2,3), GPP(4,5,6,7) */ ## u8 gfx_dev2_dev3; /* for GFX Core initialization REFCLK_SEL */ ## Don't apply above patch about rs690/chip.h before every board has been fixed. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-15Fix Kconfig for technexion/tim5690.Libra Li
Signed-off-by: Libra Li <libra.li@technexion.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-15Add CONFIG_GENERATE_* for tables so that the user can select which tables notMyles Watson
to build, but by default all the tables that are available are built. Make PIRQ table build for qemu. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-15Add Kconfig support for kontron/kt960.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4777 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-14White space and typo fixes. This makes it easier to compare the s2895 & s2892.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4773 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-14Use CAR ck804 code with the s2892.Myles Watson
Reset the s2891 so the HT speed gets updated. Remove some PANTA comments. Add SATA init from non-CAR version. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4771 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-13White space change in preparation for a patch to unify handling of ck804.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4770 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-13Revert some garbage that snuck into my trivial change, correct a spelling error.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4769 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-13Remove a couple more warnings. Trivial.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4768 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-13Add support for the MSI MS-6156 board.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4767 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-13Fix kontron/kt690 build.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4766 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-13This patch support for the Technexion Tim-5690 mainboard.Libra Li
It's an embedded AMD RS690/SB600 mainboard. http://www.technexion.com/index.php/tim-5690 Myles added Kconfig support. Signed-off-by: Libra Li <libra.li@technexion.com> Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4765 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-13This patch adds (initial) support for the Kontron KT690 mainboard. Stefan Reinauer
It's an embedded AMD 690/SB600 mainboard with a Mobile Sempron CPU. Issues with this port: - hangs early during "Starting Windows" with Windows 7, after loading all the drivers - sound is untested and probably not working - powernow seems to be not working Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-13Fix obvious typos (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4763 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-12Make fam10 build (but not boot due to bootblock size problems.)Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4762 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-11Remove useless udelay() duplication.Uwe Hermann
Abuild-tested for the boards that are touched. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4760 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-11HAVE_ACPI_TABLES cleanups for kconfig:Uwe Hermann
- Add "select HAVE_ACPI_TABLES" for boards which need it. - Drop sections which set HAVE_ACPI_TABLES to 'n', that's the default. - Convert sections which set HAVE_ACPI_TABLES to 'y' to the shorter "select HAVE_ACPI_TABLES". Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4759 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-10Drop "select CONSOLE_SERIAL8250" from QEMU, it's default-y anyway.Uwe Hermann
Tested on QEMU. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4757 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-09Add const to get rid of some warnings when passing quoted strings.Myles Watson
Remove an unused extern declaration. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4756 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-09This change allows us to see the spd on the s850, finally. Ronald G. Minnich
There is an i2c mux out there. We found it using a user level program that, as usual, began by inverting all gpios until we found out what we needed to know. In the end, we just set up the GPIOs as the factory bios does. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-09Remaining boards are Kconfig'd now. Whether they workPatrick Georgi
or not still depends on how close the configuration options are to what they should be. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-09More Kconfig-supported boards, and also kconfig supportPatrick Georgi
for amd/socket_AM2R2, amd/socket_939, drivers/ati/ragexl Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-09More kconfig cleanups:Uwe Hermann
- Use "default n" for all components that shall be "select"ed. - Use "0x0" instead of "0" for hex variables for clarity and to reduce the risk of people passing integer instead of hex values to such variables. - Add TODO comments for boards that have irq_tables.c but don' set CONFIG_HAVE_PIRQ_TABLE = 1. Someone with the hardware should test enabling. - ASUS M2V-MX SE doesn't have irq_tables.c so don't define IRQ_SLOT_COUNT in its Kconfig file. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4749 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-08Fix CS5535 build for kconfig, more kconfig boards (lippert, artec)Patrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4748 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-08This dialogue on email was useful and hence included. Ronald G. Minnich
failover.inc MUST come after enable_sse or your CPU will hang. > Can you say why? yes. if you compile failover.c with romcc options that include sse, then you'll see code like this in failover.inc: mov eax, %xmm0 This will hang if you have not first enabled sse. Verified yesterday on the dell s1850. > > Does it hang in the SSE code or in the failover code? It will hang in failover code, if that code was compiled with sse enabled AND if the sse registers are used. > > Does this mean that failover requires SSE in order to work? It may or it may not. But if you compile it with romcc options that include sse, and it uses sse without sse being enabled, it will hang. This is a particularly nasty bug in that the failover code is not guaranteed to compile in a way that sse is used, even if sse is enabled; hence, this could be very hard to catch. I'm lucky this bug appeared as soon as it did. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4746 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-08Disable x86emu for via based boards which bringPatrick Georgi
their own vgabios.c Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4744 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-08More kconfig:Patrick Georgi
AMD LX AMD SC520 boards by iei, pcengines, technexion, technologic, thomson Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-08Kconfig: AMD Fam10, all Tyan boards.Patrick Georgi
Fam10 doesn't build due to size constraints at this time. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4741 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07Emergency fix. Failover.inc can end up with code that uses sse. It has Ronald G. Minnich
to be run AFTER SSE is set up. I just had this problem cause a failure today. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07Major CONFIG_IRQ_TABLE_COUNT fixing and cleanups. Some of these boardsUwe Hermann
and PIRQ tables were actually wrong, I cannot imagine they ever worked properly. - Use CONFIG_IRQ_TABLE_COUNT in all irq_tables.c files instead of hard-coded numbers. - Make all CONFIG_IRQ_TABLE_COUNT values in irq_tables.c match Options.lb. - Make all CONFIG_IRQ_TABLE_COUNT values match the actual number of entries in the irq_tables.c file. - Set all CONFIG_IRQ_SLOT_COUNT values in src/.../Options.lb for those boards where they were set to 0 (in order to be overridden in the respective targets/.../Config.lb). This is mainly done to aid Patrick's scripts for kconfig conversion. - Fix a number of comments in irq_tables.c files. - Drop CONFIG_IRQ_SLOT_COUNT usage from boards that don't have irq_tables.c: - tyan/s1846 - asus/a8v-e_se - asus/m2v-mx_se Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4739 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07Fix trivial typo in Kconfig spotted by Peter, introduced by me.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07Get rid of early_serial, it is now a generic function in early_init. Ronald G. Minnich
Add some more enables to the s1850. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4736 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07Convert all "default y" options to "select FOO" (shorter).Uwe Hermann
Also, drop per-board CONSOLE_VGA/PCI_ROM_RUN while I'm at it, they're global options in kconfig. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4735 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07Various Kconfig fixes and improvements:Uwe Hermann
- Add helps texts to multiple user-visible Kconfig options. - Improve some menu and option names. - PAYLOAD_NONE should come before PAYLOAD_ELF, so that you scroll down (instead of up) when changing "no payload" to "ELF payload" (more intuitive, IMHO). - s/cbfs/cbfstool/. - Add some TODO items where needed. - Put GDB_STUB in a "Debugging" menu, no options should be top-level. There'll be more debug options later, I'm pretty sure. - Start converting help texts which are not user-visible to #-comments. - Re-order some options for more intuitive menus. - Set ARCH_X86 and ARCH_POWERPC to "default n", each boards selects them. - "Maximum reboot count" should proabably not be user-selectable, or at most if CONFIG_EXPERT (yet to be added) is enabled. It does definately not need its own "Misc options" menu. - Set PCI_ROM_RUN and VGA_ROM_RUN to "default y", most users will want to run option ROMs. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07Fix intel board build on kconfig. MAX_CPUS was missingPatrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4733 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07Kconfig:Patrick Georgi
- Add AMD Socket 754, - Fix MCP55 boards (romstrap) - Implement remaining MSI boards Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07Enable full ROM access on AMD CS5530(A) (needed for CBFS).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4731 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07More boards in kconfig, and moved -O2 flag for romcc intoPatrick Georgi
ROMCCFLAGS, so boards can override it where necessary. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4730 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-06UseUwe Hermann
select UDELAY_TSC select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 for all 440BX and i810 boards as per Options.lb. The UDELAY_IO / TSC / LAPIC / HPET setup will probably be checked and improved later when the kconfig transition is done. For now we keep the same values as in Options.lb. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4729 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-06Various fixes to Kconfig: All kconfig-boards should have aPatrick Georgi
complete set of variables now, though they might still have the wrong values. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-06Remove duplicate device trees for Tyan s289x. Remove pre-CBFS statements.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-05PCI_ROM_RUN and CONSOLE_VGA are global options in Kconfig andUwe Hermann
should not be set in per-mainboard Kconfigs. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-04The new CBFS based build system requires the whole ROM to be accessibleUwe Hermann
in very early stages, otherwise the boot may hang like this because the CBFS headers cannot be found/accessed: Uncompressing coreboot to RAM. Jumping to image. Check CBFS header at fffedfe0 magic is ffffffff ERROR: No valid CBFS header found! CBFS: Could not find file fallback/coreboot_ram Jumping to image. This patch enables full ROM access on all 440BX boards right after the serial init (and before CBFS headers are parsed). Build-tested and runtime-tested on ASUS P2B-F. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-04This does away with CONFIG_ROM_PAYLOAD_START and CONFIG_PAYLOAD_SIZE.Patrick Georgi
Both were only really used in pre-cbfs, as the payload's size isn't relevant for the build process anymore. Various calculations in {no,}failovercalculation.lb are adapted accordingly. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-04Add initial kconfig support for all AMD GX1 boards.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-03Remove another FAILOVER variable. (trivial)Patrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-03Add gigabyte/m57sli support to Kconfig.Harald Gutmann
Whitespace fixes to devicetree.cb Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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