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2021-01-18mb/purism/librem_cnl: Update HDA verbs for Librem MiniMatt DeVillier
Disable all NIDs other than those for the front combo jack. Adjust attributes to match jack physical location, appearance, etc. Correct group number for verbs for HDMI output. Test: run hdajackretask, verify NID characteristics correct for each verb. Verify headphone detection and output functional. Change-Id: If9fca5d9795d56bd38c8ea47f8de985c14ac8fab Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49464 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18mb/google/dedede/var/sasuke: Disable PCIE RP8 and CLKSRC3Seunghwan Kim
This change disables unused PCIE RP8 and CLKSRC3. Without this change sasuke cannot enter into s0ix properly. BUG=b:176862270 TEST=Built and verified entering s0ix Change-Id: I0828813ed7924669cb0ff97be2565579762c810f Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49300 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jamie Chen <jamie.chen@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18mb/google/dedede/var/sasuke: Add USB2 PHY parametersSeunghwan Kim
This change adds fine-tuned USB2 PHY parameters for sasuke. BUG=176060155 TEST=Built and verified USB2 eye diagram test result Change-Id: Id374ed238d92077ca28c1162fd9f070029ee71bd Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49321 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18mb/google/volteer/var/elemi: Configure USB2 portsWisley Chen
Configure the USB2 port 3/4/9 1. USB2 port3 assign to WWAN, and elemi have no WWAN. 2. USB2 port4/port9 connect to Type-C C1/C0 BUG=b:177483059 TEST=emerge-volteer coreboot Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I9affc69cc325b5eb0219b50bfe46f66eb0bb2016 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49473 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18ACPI: Select ACPI_SOC_NVS only where suitableKyösti Mälkki
Having some symmetry with <soc/nvs.h> now allows to reduce the amount of gluelogic to determine the size and cbmc field of struct global_nvs. Since GNVS creation is now controlled by ACPI_SOC_NVS, drivers/amd/agesa/nvs.c becomes obsolete and soc/amd/cezanne cannot have this selected until <soc/nvs.h> exists. Change-Id: Ia9ec853ff7f5e7908f7e8fc179ac27d0da08e19d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao
2021-01-16mb/google/volteer: do UART pad config at board-levelMichael Niewöhner
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to the early UART gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Also switch to `bootblock_mainboard_early_init` to configure the pads in early bootblock before console initialization, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: I5e07584d7857052c7a9388331a475f5a073af038 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-16mb/system76/lemp9: do early pad configuration in early bootstageMichael Niewöhner
Do early pad configuration in early bootblock before console init, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: Ie122a441145383b820d96e32ce1581dfc27fa57b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-01-15build system: Always add coreboot.pre dependency to intermediatesPatrick Georgi
They all operate on that file, so just add it globally. Change-Id: I953975a4078d0f4a5ec0b6248f0dcedada69afb2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-15mb/amd/mandolin: Clean up IRQ numbersRaul E Rangel
We no longer need the IO-APIC assignments since we use the GNB IO-APIC. We were also missing the E-H IRQ mapping. I also renumbered them since IRQ 8 is used by the rtc. TEST=none BRANCH=zork Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia956ae457669aeda6fa49e127373aad3807f7b9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/49368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-15mb/google/zork: update USB 2.0 controller Lane Parameter for dirinbozKevin Chiu
Enhance USB 2.0 M/B C0, DB C1 A1 port: HS DC Voltage Level(TXVREFTUNE0): 0xe COMPDISTUNE(COMPDISTUNE0): 0x7 BUG=b:165209698 BRANCH=zork TEST=emerge-zork coreboot Change-Id: I371e4295c2ee161096f0a277c0c649bf217269b2 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-15mb/google/zork/var/shuboz: update STAPM add telemetry settingKane Chen
1. Modify STAPM time constant 2500 to 1400. 2. Add telemetry setting: VDD Slope : 30518 VDD Offset: 435 SOC Slope : 22965 SOC Offset: 165 BUG=b:177399751 BRANCH=master TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I251029389c10ee0f17f368b1c00ac666d372fc3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/49386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-01-15mb/google/zork: update DRAM table for berknipKevin Chiu
Add Hynix DDR4 DRAM H5ANAG6NCJR-XNC, index was generated by gen_part_id BUG=b:176313722 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: Ia1947fa158a1113c4a0b1a0d55f657ddaac43382 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-01-15mb/google/kukui: Add new ddr architecture support for kukuiShaoming Chen
Two configuration files are added: 1. H9HCNNNFAMMLXR-NEE-8GB: new byte mode 2. MT53E1G32D2NP-046-4GB: new single rank mode Also initialize the rank number field 'rank_num' for all configs. BUG=b:165768895 BRANCH=kukui TEST=DDR boot up correctly on Kukui Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> Change-Id: I1786c1e251e8d6e110cbdce79feeb386db220404 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49108 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-15mb/google/zork/var/vilboz: Add WiFi SAR for VilbozFrank Wu
The fw_config field SPI_SPEED is not used for zork devices. To define SAR config, use the fw_config bit[23..26]. Then vilboz can loaded different WiFi SAR table for different SKUs. BUG=b:176858126, b:176751675, b:176538384 BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage, then verify that tables are in CBFS and loaded by iwlwifi driver. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I5ba98799e697010997b515ee88420d0ac14ca7ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/49296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-15mb/google/volteer/var/voema: Configure USB2 ports for Type CDavid Wu
Based on voema schematics, two USB2 ports 3 and 5 are assigned to type C connectors on Voema board. BUG=b:177483061 b:172535001 TEST=Build and boot Voema. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I12cef85595e511801ab9c563ae4aa26e25875679 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-15mb/siemens/mc_apl1: do LPC/eSPI pad configuration at board-levelMichael Niewöhner
Do LPC/eSPI pad configuration at board-level to match other platforms. Early gpio configuration was done in romstage, while LPC pads were configured in bootblock. Instead of adding another dedicated gpio table for bootblock, move early gpio configuration completely to bootblock on these boards. This won't hurt, since there is no code touching the pads in between. The soc code gets dropped in CB:49410. Change-Id: I2a614afb305036b0581eac8ed6a723a3f80747b3 Tested-by: Mario Scheithauer <mario.scheithauer@siemens.com> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-01-15cpu/intel/haswell: Factor out ACPI C-state valuesAngel Pons
There's no need to have them in the devicetree. ACPI generation can now be simplified even further, and is done in subsequent commits. Change-Id: I3a788423aee9be279797a1f7c60ab892a0af37e7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46908 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-15mb/intel/baskingridge: Replace invalid C-state valuesAngel Pons
Basking Ridge is not ULT, thus does not support C-states deeper than C7. Replace them with the values used by all other Haswell non-ULT boards to allow subsequent commits to cleanly factor them out of the devicetree. Change-Id: Ife34f7828f9ef19c8fccb3ac7b60146960112a81 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46907 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-15mb/google/dedede/var/boten: Update LTE GPIO configurationKarthikeyan Ramasubramanian
LTE module is not expected to be powered off during warm reset. Hence configure the LTE_PWR_OFF_ODL (GPP_A10) gpio pad reset configuration to PWROK and set the TX state to 1. BUG=b:163100335 BRANCH=dedede TEST=Verified through the waveforms that power sequence is meeting the LTE module requirements. Change-Id: I8676da6186559288aabe078b6158fc01075c7b41 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-15mb/google/dedede/var/metaknight: Add LTE power on/off sequenceTim Chen
LTE module used in metaknight has a specific power on/off sequence. GPIOs related to power sequence are: * GPP_A10 - LTE_PWR_OFF_R_ODL * GPP_H17 - LTE_RESET_R_ODL 1. Power on: GPP_A10 -> 20ms -> GPP_H17 2. Power off: GPP_H17 -> 10ms -> GPP_A10 3. Warm reset: GPP_A10 keeps high, GPP_H17 goes low at least 2ms Configure the GPIOs based on these requirements. BUG=b:173671094 TEST=Build and boot Metaknight to OS. Ensure that the LTE module power sequence requirements are met. Change-Id: Ibff16129dfe2f1de2b1519049244aba4b3123e52 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-15mb/facebook/fbg1701/Kconfig: Remove dependency for USE_VENDORCODE_ELTANFrans Hendriks
make olddefconfig on other projects using USE_VENDORCODE_ELTAN results in error. USE_VENDORCODE_ELTAN unmet direct dependencies. Remove dependency on VBOOT for USE_VENDORCODE_ELTAN. TEST = Build and boot on Facebook FBG1701 Change-Id: I5881c334955c73ae0f1a693f95ceb1aee62ee898 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2021-01-15mb/google/asurada: Implement HW reset functionYidi Lin
TEST=call do_board_reset() manually. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I355f71e731f1045cd80a133cd31cf4d55f14d91f Reviewed-on: https://review.coreboot.org/c/coreboot/+/49237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-14mainboard/volteer: Configure UsbTcPortEn valueBrandon Breitenstein
The default value is not sufficient to correctly configure the Type-C ports as it has all ports disabled by default. On Volteer ports 0 and 1 are enabled so setting this value to 0x3 and correctly keeping the IomPortPadCfg values at 0 for ports that have a retimer and ports that are not configured. These values were set to 0x90000000 to avoid s0ix issues which arose from the UsbTcPortEn value being incorrect. BUG=b:159151238 BRANCH=firmware-volteer-13672.B TEST=Built image for Voxel and verified that s0ix cycles complete without any issues Change-Id: Ib4f2bd0f68debd4e97ccaab9e1d8a873dc4e4d9f Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48814 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-14build system: Structure and serialize INTERMEDIATEPatrick Georgi
Target added to INTERMEDIATE all operate on coreboot.pre, each modifying the file in some way. When running them in parallel, coreboot.pre can be read from and written to in parallel which can corrupt the result. Add a function to create those rules that also adds existing INTERMEDIATE targets to enforce an order (as established by evaluation order of Makefile.inc files). While at it, also add the addition to the PHONY target so we don't forget it. BUG=chromium:1154313, b:174585424 TEST=Built a configuration with SeaBIOS + SeaBIOS config files (ps2 timeout and sercon) and saw that they were executed. Change-Id: Ia5803806e6c33083dfe5dec8904a65c46436e756 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49358 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-14mb/amd/majolica: use integrated UART as consoleFelix Held
Change-Id: Ic6dcbe999234f233fbac8fbdb06d22c8577b1a40 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-14soc/amd/stoneyridge: use SOC_AMD_COMMON_BLOCK_UARTFelix Held
Since the functions that get called by the coreboot console initialization code aren't in the SOC-specific code anymore, the SOC's uart.c can be included unconditionally in the build now. This also replaces the STONEYRIDGE_UART Kconfig option with the common AMD_SOC_CONSOLE_UART one. Change-Id: I09c15566a402895d6388715e8e5a802dc3c94fdd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49375 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-14mb/google/dedede/var/boten: Support ELAN i2c-hid touchscreen for botenflexStanley Wu
Update ELAN i2c-hid touchscreen configuration BUG=b:172517685 BRANCH=dedede TEST=Verify touchscreen is working fine on botenflex Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: Ia7c81fd0a772968ec32406f1e366a90481fc5ad8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-13mb/google/kahlee,zork: Use mainboard_fill_gnvs()Kyösti Mälkki
Change-Id: Ic9cdcc497bf1a9f5bfed5e6d95040bfa602b0b89 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48732 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-13mb/google/volteer/variants/delbin: Update PL1 min and max for DelbinDeepika Punyamurtula
Update PL1 min and max values for Delbin systems BUG=b:168958222 BRANCH=None TEST=Build and verify on delbin system Signed-off-by: Deepika Punyamurtula <deepika.punyamurtula@intel.com> Change-Id: I2152f0dbeb0ae463b78464571b6c434830f0082a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
2021-01-13mb/google/volteer: Add CSE Lite SKU support to Copanohao_chou
This will allow CSE RW FW updates and also fixes the problem where no sound is emitted from the speakers. BUG=b:174338903 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com> Change-Id: I875f6b32c4053ef6d23ad7606cd35a129a78c306 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49290 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-12mb/google/brya: Initialize overridetree.cbEric Lai
Initiate overridetree.cb based on latest schematic. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I31e5ac1703476083ac71dac30b0a3299b38384c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-12mb/google/brya: Add gpio tableEric Lai
Follow latest schematic to fill gpio table. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3a983605b5139ff8510a0cf225e6564b9215cb1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/48290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-12mb/google/volteer: Configure Voxel USB2 ports for Type CJohn Zhao
Two USB2 ports 4 and 9 are assigned to type C connectors on Voxel board. This update configures these USB2 ports for Type C which will allow USB2 port reset message upstream from PCH to CPU to recover a USB3 device that downgraded to USB2 to upgrade back to USB3. BUG=b:176575892 TEST=Booted to kernel on Voxel board and verified usb2 port reset message enable bits through pch xhci_mmio_base + R_XHCI_MEM_U2PRM_U2PRDE where the offset register R_XHCI_MEM_U2PRM_U2PRDE has value 0x92f4. Validated various USB3 devices enumeration. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ia370a449a41701e690c1c507d70bedfce2076a65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.corp-partner.google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2021-01-12mb/google/zork/var/vilboz: Fix FW_CONFIG_SHIFT_WWAN valueJohn Su
The FW config takes 2 bits for USE_FAN[27,28]. So FW_CONFIG_SHIFT_WWAN value should be 29. BUG=b:174121847 BRANCH=zork TEST=build vilboz Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ica6d04f9c48aa0800189283608bf57416ac75cf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49236 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11mb/google/octopus: add audio codec into SSFC support for MeepTony Huang
BUG=b:171757619 BRANCH=octopus TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check whether device tree is updated correspondingly by disabling unselected one. Change-Id: I37390535e263b4b9547ad7307278e3360ba836bd Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com>
2021-01-11{soc,vc,mb}/intel: Drop support for Cannon Lake SoCFelix Singer
Drop the support for the Intel Cannon Lake SoC for various reasons: * Most people can't use coreboot on Cannon Lake, since the required FSP binaries aren't publicly available. Given that FSP binaries for several newer platforms have been released, it's very unlikely that Cannon Lake FSP will ever be released. * It seems there is no interest in this, since the reference mainboard is the only available mainboard in tree. Also, remove the related reference mainboard intel/cannonlake_rvp and its FSP headers in intel/fsp2_0/cannonlake. Change-Id: I8f698e16099acb45444b2bc675642d161ff8c237 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48775 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11mb/google/volteer: Add CSE Lite SKU support to DrobitWayne3_Wang
This will allow CSE RW FW updates and also fixes the problem where no sound is emitted from the speakers. BUG=b:176536593 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot Signed-off-by: Wayne3_Wang <wayne3_wang@pegatron.corp-partner.google.com> Change-Id: I69962a5b7c7c464280b35c834f7ee1c9b77db6fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/49197 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11mb/google/volteer: Set FORCE_PWR low at boot timeJohn Zhao
While FORCE_PWR is set high, it prevents retimer from entering low power state. S0ix failure occurs while USB4 Gatkex is connected on Port-0. This change sets FORCE_PWR(GPP_H10) low. This FORCE_PWR GPIO will be toggled by kernel through DSM method while updating retimer firmware. BUG=b:174166586 Cq-Depend: chromium:2594438 TEST=Verifed s0ix cycles with USB4 Gatkex connected on Port-0. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ie4b442e1078379c522a94bfdc00cd99e6f9b8170 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-11mb/emulation/qemu: Copy page tables to DRAM in assemblyPatrick Rudolph
To work around various bugs running KVM enabled, copy page tables to DRAM in assembly before jumping to x86_64 mode. Tested on QEMU using KVM, no more stange bugs happen: Tested on host - CPU Intel(R) Core(TM) i7-7700HQ - Linux 5.9 - qemu 4.2.1 Used to crash on emulating MMX instructions and failed to translate some addresses using the virtual MMU when running in long mode. Tested on host - CPU AMD EPYC 7401P 24-Core Processor - Linux 5.4 - qemu 4.2.1 Used to crash on jumping to long mode. Change-Id: Ic0bdd2bef7197edd2e7488a8efdeba7eb4ab0dd4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-11mb/google/dedede/var/magolor: Remove the unused touch controllerRen Kuo
Remove unused touch controller - Goodix BUG=None BRANCH=dedede TEST=build firmware Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I2a01666bc1e353e21ddf961a0eb721a0cb4013db Reviewed-on: https://review.coreboot.org/c/coreboot/+/49221 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10mb/intel/adlrvp: Update GPIOs as per latest schematicsSubrata Banik
1. GPP_D8, GPP_H23 => Remove unused GPIOs 2. GPP_E18 .. GPP_E22 => Program the correct Native Functions for GPIO Change-Id: Iedb1f8fbf5f96a9617b72ba1a6419e3fd4e331b4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49260 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10mb/intel/adlrvp: Fix FW download failed for PEG 060, 010Subrata Banik
Enable PCIE RP1 to fix DEKEL FW download failed for x4 controller (PEG 0:6:0). Enable PCIE RP3 to fix HSPHY FW download failed for x8 controller (PEG 0:1:0) BUG=b:176940923 TEST=No FSP error seen while loading DEKEL, HSPHY FW. Change-Id: I3cd8cba02a96185803a0c0d442f3d6aa495d2642 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-10soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPsSubrata Banik
List of changes: 1. Create new Kconfig MAX_CPU_ROOT_PORTS and MAX_PCH_ROOT_PORTS as per EDS. 2. Add new chip variable to enable/disable CPU PCIE RPs from mainboards. 3. Rename PcieRpEnable to PchPcieRpEnable. 4. Enable CPU RPs as below in mainboard devicetree.cb RP1: PEG60 : 0:6:0 : CPU SSD1 RP2: PEG10 : 0:1:0 : x8 CPU Slot RP3: PEG62 : 0:6:2 : CPU SSD2 Change-Id: I92123450bd7cfb2e70aae8de03053672a7772451 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49136 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10mb/google/cyan: Move board_id() to mainboard_fill_gnvs()Kyösti Mälkki
Only a google/cyan variant evalutes BDID in ASL. Change-Id: I3d839333333b4762ae5350734c85471a3c12838a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49003 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10soc/intel: Replace acpi_init_gnvs()Kyösti Mälkki
Rename these to soc_fill_gnvs() and move the callsite away from mb/. Change-Id: I760c36f65c6122103f2be98fc11ee13832c2772e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48716 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10mb/x/acpi_tables: Rename to mainboard_fill_gnvs()Kyösti Mälkki
Rename acpi_create_gnvs() functions under mb/ to reflect their changed functionality. Remove now empty mb/acpi_tables.c files. Change-Id: Ia366867ef73d1ade9805dc29b8e14b3073f44f60 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48707 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10mb/x/acpi_tables: Move EC_RW detectionKyösti Mälkki
These boards without ChromeEC do not set ACTIVE_EC_RW flag as part of the gnvs_assign_chromeos() function. Create abstraction to avoid <vendorcode/chromeos/x> include. Change-Id: Ic6029e1807fcfe7dd2c766ce8221e347b6b096f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48777 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10ACPI: Drop redundant ChromeOS setup for GNVSKyösti Mälkki
Already done in common gnvs_get_or_create() implementation once gnvs_chromeos_ptr() is defined for platforms. Change-Id: I90fa2bc28ae76da734b3f88be057435aed9fe374 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48703 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10ACPI: Drop redundant CBMEM_ID_ACPI_GNVS allocationsKyösti Mälkki
Allocation now happens prior to device enumeration. The step cbmem_add() is a no-op here, if reached for some boards. The memset() here is also redundant and becomes harmful with followup works, as it would wipe out the CBMEM console and ChromeOS related fields without them being set again. Change-Id: I9b2625af15cae90b9c1eb601e606d0430336609f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48701 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-09mb/google/parrot: Replace while-loop with do-whileFelix Singer
Fixes linter error complaining about trailing semicolon. Change-Id: I3f74f25cb2e3edcdd509abd86d80098241c05741 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-09mb/google/parrot: Let else statement follow closing braceFelix Singer
Fixes a linter error. Change-Id: I1302e32b0d52e37d9cb4503128edc7d1df1c3bd8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-09mb/google/parrot: Get rid of hard-coded function names in printksFelix Singer
Instead of hard-coding function names in strings, use the __func__ constant for better maintainability. Change-Id: I151560cd5a135e00f494eda3f9d3b592ee9d984a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-09mb/google/parrot: Fix spacing issuesFelix Singer
Add a space after each comma to fix linter issues. Change-Id: I5533c4fc7aa0e986da4350ec56b84903b3111a07 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-09mb/hp/pavilion_m6_1035dx: Replace leading spaces with tabsFelix Singer
Replace leading spaces with tabs so that linter doesn't complain. Also, remove an unneeded empty line. Change-Id: I5809c1ca13782393cb4c4051a7061186c1c144e4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-09mb/hp/pavilion_m6_1035dx: Replace (foo*) with (foo *)Felix Singer
Change-Id: Iff38caf5f4a4d25f4bafdd821c51de24f54e3ce5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-09mb/hp/pavilion_m6_1035dx: Put opening braces in previous lineFelix Singer
Put opening braces in previous line to fix linter errors. Change-Id: I7bd49393056f80ce4f6078c646db46c2a67f2381 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49234 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-09mb/hp/pavilion_m6_1035dx: Remove trailing semicolon from macroFelix Singer
Macros should not use a trailing semicolon. Change-Id: Ibbcd589c7afa72e9e468e5f4b557bb2c665bbec0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-09mb/hp/pavilion_m6_1035dx: Fix spacing issues in mptable.cFelix Singer
Align the bytes of picr_data[] and intr_data[] with 8 bytes per line and add spaces after commas so that the linter doesn't complain. Also, remove spaces before the postfix '++' operator. Built with BUILD_TIMELESS=1, coreboot.rom remains the same. Change-Id: I90bec7fdfabca6f8afd1508c673241e0742e2ee9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49191 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-09mb/asrock/h110m: Drop VR configuration from devicetreeFelix Singer
Drop VR configuration since it matches the platform defaults. Change-Id: I92007f4ff9d093c9573bb1ee13e64eb2f38af4f4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-09mb/asrock/h110m: Remove zeroed options from devicetreeFelix Singer
Built with BUILD_TIMELESS=1, coreboot.rom remains the same. Change-Id: Ic39b4c70ccb9ec21780c937322d63820064abbd1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49185 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08mb/google/volteer: Configure Delbin USB2 ports for Type CJohn Zhao
Two USB2 ports 4 and 9 are assigned to type C connectors on Delbin board. This update configures these USB2 ports for Type C which will allow USB2 port reset message upstream from PCH to CPU to recover a USB3 device that downgraded to USB2 to upgrade back to USB3. BUG=b:176575892 TEST=Booted to kernel on Delbin board and verified usb2 port reset message enable bits through pch xhci_mmio_base + R_XHCI_MEM_U2PRM_U2PRDE where the offset register R_XHCI_MEM_U2PRM_U2PRDE has value 0x92f4. Validated various USB3 devices enumeration. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Idb3ce949e1ecf3adc7615e0af79a38a0cc9be18f Reviewed-on: https://review.coreboot.org/c/coreboot/+/49202 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08mb/google/octopus: add audio codec into SSFC support for BobbaMarco Chen
BUG=b:174118027 BRANCH=octopus TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check whether device tree is updated correspondingly by disabling unselected one. Signed-off-by: Marco Chen <marcochen@google.com> Change-Id: Id37c4c5716ade0851cfcb24e12b390841e633ac9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
2021-01-08mb/google/asurada: Support audioTzung-Bi Shih
- Turns audio-related things power on. - Selects I2S pin-muxing. - Exposes GPIO "speaker enable" for switching on and off. BUG=b:176856418 Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: If595657bbddad85bc9a154b3648bae1190cb00b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-08mb/google/dedede/var/sasuke: Add internal USB camera supportSeunghwan Kim
This change adds internal USB camera into devicetree for sasuke BUG=None TEST=Built and checked camera device existence with lsusb Change-Id: I51b9bb174205d984f1d060afd603f1d087095645 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49162 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08mb/google/dedede/var/sasuke: Enable ELAN touchpadSeunghwan Kim
This change adds ELAN touchpad into devicetree for sasuke. BUG=None TEST=Built and verified touchpad function Change-Id: If9c25f23ee1c0e88382fff036f77a6753775b81e Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-08mb/google/dedede/var/sasuke: Enable audio featureSeunghwan Kim
This change adds DA7219 audio codec and MAX98360A amplifier for sasuke. BUG=None TEST= Built and heared speaker sound on OS Change-Id: Ib48eb74fbfe171d46d0d23859057ba169b56bde2 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-08mb/google/dedede/var/sasuke: Configure GPIO NC padsSeunghwan Kim
Configure GPIO NC pads for sasuke. BUG=b:172104731 TEST="FW_NAME=sasuke emerge-dedede coreboot" Change-Id: I3bf8f97708536010da82402ea3d49e387e732d61 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-08mb/asrock/h110m: Drop DEVICETREE from KconfigFelix Singer
Drop DEVICETREE from Kconfig since it matches the default value. Built with BUILD_TIMELESS=1, coreboot.rom remains the same. Change-Id: Idbcd49cca6494ae2da0f364c24638d7ca11911da Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-01-08mb/clevo/cml-u: Drop VGA_BIOS_FILE from KconfigFelix Singer
It doesn't make sense to configure that filename in Kconfig, since the filename can be changed by the user. So remove it. Change-Id: I3eed05637da29096bc1d134505d7335db5db1439 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49138 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08mb/google/volteer: Update copano device treehao_chou
Update device tree override to match schematics. BUG=b:175896481 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com> Change-Id: I1fb006d750bb2d670885ec8ccc627436c5078072 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-08mb/google/volteer: Add GPIO to copano supporthao_chou
Add support for gpio driver for copano BUG=b:175896481 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com> Change-Id: I1e0f730c9865ed77c7071245b071315a9c6ea4c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48951 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08mb/google/volteer: Copano: Update SPD tablehao_chou
Add memory table to "mem_list_variant.txt", and command to generate files: go run ./util/spd_tools/lp4x/gen_part_id.go src/soc/intel/tigerlake/spd src/mainboard/google/volteer/variants/copano/memory/ src/mainboard/google/volteer/variants/copano/memory/mem_list_variant.txt DRAM Part Name ID to assign MT53D512M64D4NW-046 WT:F 0 (0000) H9HCNNNCRMBLPR-NEE 0 (0000) MT53D1G64D4NW-046 WT:A 1 (0001) H9HCNNNFBMBLPR-NEE 2 (0010) BUG=b:175896481 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com> Change-Id: I2ace17e8fff12d3f5de15a35f609265d8b6ed6b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48948 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08mb/google/zork: Unmap FCH IO-APIC PCI interruptsRaul E Rangel
Now that the _PRT generates a GNB IO-APIC routing table we no longer need to route the PCI interrupts through the FCH IO-APIC. This change unmaps the IRQs since they are no longer used. BUG=b:170595019 TEST=Boot with `pci=nomsi amd_iommu=off` and verify /proc/interrupts Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3467934bfcac14311505bec49a12652490554e6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/48669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-08pineview boards: Drop MAINBOARD_HAS_NATIVE_VGA_INITAngel Pons
Already selected from northbridge Kconfig. Change-Id: I5a30769b4186041a15fd1264bb0d6efa32cb6eb4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49182 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08mb/google/dedede: Enable "FastPkgCRampDisable" upd for noise mitigationMaulik V Vaghela
As part of acoustic noise mitigation calibration, we need to enable FastPkgCRampDisable upd along with slew rate = 1. This values has been derived based on noise calibration done. Please refer document 575216 for procedure. BUG=None BRANCH=dedede TEST=correct value has been programmed and slew rate measurement is correct on scope. Change-Id: Ie42c8ab647ff42fa043b6f717a9834f9b9c551f6 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-01-07mb/google/zork: Decrease stamp_boost parameter for dirinbozKevin Chiu
Original Stamp_boost parameter will cause boost time over 2500sec(3960sec) To pass balance performance and skin temperature test, decrease stamp_boost: 2500 -> 1640 BUG=b:175364713 TEST=1. emerge-zork coreboot 2. run balance performance and skin temperature test Change-Id: I44f086af6b5dd552efd2bd1ef4db0d69b652826d Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-01-07mb/google/dedede: Add support for charger throttlingSumeet Pawnikar
Add charger current throttling support for dedede baseboard BUG=None BRANCH=None TEST=Built and tested on boten system Change-Id: I79edba579249111294a982590660196f05be7eaf Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49083 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07mb/asrock/h110m: Remove MAINBOARD_POWER_ON_AFTER_POWER_FAILMartin Roth
The MAINBOARD_POWER_ON_AFTER_POWER_FAIL symbol was removed in Commit 9faae2b939. The default is currently to keep power off after a power failure. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ib2ef450f5c64f663b9aa88f8870250e92898e308 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47671 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07mb/google/volteer/var/elemi: Tune i2c frequencyWisley Chen
Tuning i2c frequency for elemi I2C0: 396.6 KHz I2C1: 395.9 KHz I2C5: 397.1 KHz BUG=b:176794161 BRANCH=volteer TEST=emerge-voleteer coreboot, and measure i2c clock. Change-Id: I23b04a9b5ff8873d9de12e762e8e2786ef474ac0 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-07mb/google/dedede/var/metaknight: update Goodix touch screen sequenceTim Chen
Update Goodix touch screen reset delay time to 180ms. BUG=b:176213670 TEST=Build and boot Metaknight to OS. Change-Id: I5801a36fb7c03b23046df16b1eaf4c548241bba5 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-07mb/google/zork: Modify variant to Shuboz supportKane Chen
1. Add ELAN touchscreen/touchpad to overridetree.cb 2. Follow Dalboz setting to add variant.c BUG=b:174528384 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ic3193ca7957251841e75a7e5c7a16fc5047919fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/48001 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07mb/intel/jasperlake_rvp: Fix building with CONFIG_CHROMEOS unsetMatt DeVillier
Make EC_GOOGLE_CHROMEEC_SWITCHES depend on VBOOT, rather than force selecting it. Change-Id: If96b2a935d2f7388a24be7d8e65c7dfc2c89a0fc Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-07mb/intel/adlrvp: Fix building with CONFIG_CHROMEOS unsetMatt DeVillier
Make GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC depend on VBOOT, rather than force-select it. Change-Id: I0ec418d4182865636b6350f1ee151420d8e02c33 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-01-07mb/google/lindar: Fix building with CONFIG_CHROMEOS unsetMatt DeVillier
Make CHROMEOS_DSM_CALIB depend on CHROMEOS, rather than force-select it. Change-Id: I4c3fd04ec00e0787381c58810938dd48f414635c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-07soc/intel/common/cse: Drop dependency on CHROMEOS for SOC_INTEL_CSE_LITE_SKUMatt DeVillier
The CSE lite SKU has 2 CSE firmware boot partitions vs 3 for the "normal" SKU; this has nothing to do with building for ChromeOS or not, and by having this dependency, boards with select the CSE lite SKU are unable to build with CONFIG_CHROMEOS unset due to Kconfig dependency issues. Test: build google/wyvern with CONFIG_CHROMEOS not set. Change-Id: I6959f35e1285b2fab7ea1f83a5ccfcb065c12397 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-07mb/google/puff/var/dooly: Config I2C0 SerialIoDevModeTony Huang
I2C0 has amplifier connection, thus set it to PchSerialIoPci. BUG=b:170273526 BRANCH=puff TEST=Build and check PCH serial IO config is set I2C0 to Mode 1 Change-Id: I9540f7b5538d37de53bcf43531488d714874a565 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2021-01-07mb/razer/blade_stealth_kbl: Remove comments with pad functionsMaxim Polyakov
Remove these comments, because it does not contain useful information that helps to understand the circuit, which we do not have. Tested with BUILD_TIMELESS=1, Razer Blade Stealth, remains identical. Change-Id: I8a8450493ceebe97ac03b4134adc46b01328a1b6 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-07mb/google/dedede/var/magolor: modify raydium touch screenRen Kuo
modify raydium touch screen power on timing to meet requirement BUG=b:174280232 TEST=build firmware and measured the timing Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I3ecc9d8e21f8c76e9e96cf050dcde83c3c4f4ea7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48971 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07mb/google/dedede/var/metaknight: Configure I2C high and low timesTim Chen
Configure the I2C bus high and low times for port0,2 and 4 I2C buses. BUG=b:176519792 TEST=Measured the I2C bus frequency lower than 400 KHz. Change-Id: Ieed038c93f0972c06cb3fa311742dd22ac2e875d Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-07mb/google/dedede/var/madoo: Update Goodix touchscreen power sequenceDtrain Hsu
Follow Goodix datasheet (GT7375 Programming Guide_Rev.0.1.pdf and GT7375P Programming Guide_Rev.0.6.pdf) to tune touchscreen power sequence. Increase reset_delay_ms from 120ms to 180ms. BUG=b:176511605 BRANCH=dedede TEST=Build and boot Madoo to OS Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Iae35e4da31a3c3afd24c7daf81a5a3e762acd3b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-07mb/google/dedede/var/boten: Configure I2C high and low timeStanley Wu
Configure the I2C bus high and low time for all enabled I2C buses. BUG=b:168783630 TEST=Measured the I2C bus frequency reduce to 387 KHz. Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I37403dd3ac3c9320398207d2111e1ddb73d6a130 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-07mb/google/dedede/var/lantis: Config I2C high and low time for touchscreen/audioTony Huang
Config I2C high / low time in device tree to ensure I2C CLK runs accurately at I2C_SPEED_FAST (400 kHz). These tuning value is applied from touchpad as a base line, and EE measured touchscreen/audio runs at 399/396.7kHz after tuning. BUG=b:173709409 BRANCH=dedede TEST=Build and check after tuning I2C clock is under 400kHz Change-Id: I970d69e6361d7cf6fcfc4e5b0b3c5fbfa885367c Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-07mb/google/dedede/var/lantis: Config I2C high and low time for touchpadTony Huang
BUG=b:173709409 BRANCH=dedede TEST=EE measured result is 390.8kHZ Change-Id: I7a6475fd29d4c9f8efa78a42a112b5565511b939 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-07mb/google/zork/var/vilboz: Fix Goodix touchscreen power sequenceFrank Wu
According Goodix GT7375P Programming Guide_Rev.0.6, increase the stop delay time from 100 ms to 160 ms. The power sequence is not met with the latest guide_rev.0.6. BUG=b:176270381 BRANCH=zork TEST=Confirm the measured waveform complies with Goodix touchscreen spec. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I687ffa2eb13a9ddecb3045c5e1540b94417329ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/48907 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-06soc/intel/broadwell: Move MAX_CPUS from mb to SoCFelix Singer
All Broadwell boards use 8 for MAX_CPUS, so this option can be factored out into SoC Kconfig. Change-Id: I311b95ea75a7c6b76b32c7197a0cec86db644234 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49122 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-06soc/intel/skylake: Move MAX_CPUS from mb to SoCFelix Singer
Configure MAX_CPUS in SoC Kconfig with 8 as default value and remove it from every mainboard where 8 is used. Change-Id: I825625bf842e8cd22dada9a508a7176e5cc2ea57 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49105 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-06mb/intel/wtm2/Kconfig: Limit MAX_CPUS to 8Angel Pons
Haswell and Broadwell have at most 8 threads. Change-Id: Idcccf22addb6e15d7c55b9816141af47d6186cca Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46952 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-06mb/google/volteer/var/voema: Update Aux settings for Port 0David Wu
On Voema port 0 (MB PORT) does not have a retimer so the port needs to be configured for the SOC to handle Aux orientation flipping. BUG=b:176462544 TEST=tested on voema Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I3d31a5b848f56126f8ffe2babb29085471e8224f Reviewed-on: https://review.coreboot.org/c/coreboot/+/48976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2021-01-06mb/amd/mandolin/mainboard: Remove unused pirq_dataRaul E Rangel
This table was wrong. It's also produced by the SoC code now. BUG=b:170595019 TEST=None Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifcc406591abf88ebdb5ed972614c3a6901721bac Reviewed-on: https://review.coreboot.org/c/coreboot/+/48667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-06mb/google/zork/mainboard: Remove unused pirq_dataRaul E Rangel
This table was wrong. It's also produced by the SoC code now. BUG=b:170595019 TEST=Verify PCI IRQ: log messages Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I008b6896064672f9d45a8e12f6cfc62c0cc41536 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-16 01:05:59 +0000