Age | Commit message (Collapse) | Author |
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2006 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Special version for HDAMA rev G with 33Mhz test and reboot out.
- Support for CPU rev E, dual core, memory hoisting,
- corrected an SST flashing problem. Kernel bug work around (NUMA)
- added a Kernel bug work around for assigning CPU's to memory.
r2@gog: svnadmin | 2005-08-03 08:47:54 -0600
Create local LNXI branch
r1110@gog: jschildt | 2005-08-09 10:35:51 -0600
- Merge from Tom Zimmerman's additions to the hdama code for dual core
and 33Mhz fix.
r1111@gog: jschildt | 2005-08-09 11:07:11 -0600
Stable Release tag for HDAMA-1.1.8.10 and HDAMA-1.1.8.10LANL
r1112@gog: jschildt | 2005-08-09 15:09:32 -0600
- temporarily removing hdama tag to update to public repository. Will
reset tag after update.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2003 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1992 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1984 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1983 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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1. x86_setup_mtrr take address bit.
2. generic ht, pcix, pcie beidge...
3. scan bus and reset_bus
4. ht read ctrl to decide if the ht chain
is ready
5. Intel e7520 and e7525 support
6. new ich5r support
7. intel sb 6300 support.
yhlu patch
1. split x86_setup_mtrrs to fixed and var
2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource
3. in_conherent.c K8_SCAN_PCI_BUS
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Yinghai Lu <yhlu@tyan.com>
add eswar code in intel car to disable Hyperthreading
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1980 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Yinghai Lu <yhlu@tyan.com>
write_pirq_routing_table for x86
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1979 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Li-Ta Lo <ollie@lanl.gov>
More Via EPIA
more via epia stuff, including the trival but fatal bug in auto.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1978 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Li-Ta Lo <ollie@lanl.gov>
S4880 mainboard Config.lb
Comment in the Config.lb shoud be '#' rather than the C++ '//'.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1977 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Li-Ta Lo <ollie@lanl.gov>
auto.c and failover.c
convert mainboard auto.c and failover.c to post DOM era
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1976 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Yinghai Lu <yhlu@tyan.com>
remove junk in s2885 cache_as_ram_auto.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1974 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1972 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Yinghai Lu <yhlu@tyan.com>
intel car to x86 car
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1971 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Ronald G. Minnich <rminnich@lanl.gov>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Yinghai Lu <yhlu@tyan.com>
more safe stack in ram for cache_as_ram
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1969 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Yinghai Lu <yhlu@tyan.com>
cache_as_ram for AMD and some intel
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Ronald G. Minnich <rminnich@lanl.gov>
This now boots to the point of passing the memory test in auto.c. But: we still don't have it working after the "Jumping to LinuxBIOS" step
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1966 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Ronald G. Minnich <rminnich@lanl.gov>
this is a version that does not fail, but memory is still not up
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Ronald G. Minnich <rminnich@lanl.gov>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Ronald G. Minnich <rminnich@lanl.gov>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1963 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Ronald G. Minnich <rminnich@lanl.gov>
sc520 fails after NOP
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Ronald G. Minnich <rminnich@lanl.gov>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1961 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Li-Ta Lo <ollie@lanl.gov>
Onboard VGA for HDAMA
Added onboard VGA support for Arima/HDAMA
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1957 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Li-Ta Lo <ollie@lanl.gov>
ibm e325
Bring imb e325 to post device object model era
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1956 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Li-Ta Lo <ollie@lanl.gov>
emulator update
x96emu update from Paulo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Li-Ta Lo <ollie@lanl.gov>
emulator update
Correction to the reduce emulator from Paulo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Yinghai Lu <yhlu@tyan.com>
s2881 dual core config
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1951 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Yinghai Lu <yhlu@tyan.com>
AMD D0/E0 Opteron new mem mapping support, AMD E Opteron mem hole support,AMD K8 Four Ranks DIMM support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Yinghai Lu <yhlu@tyan.com>
remove lsi/53c1030 in MB Config
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Yinghai Lu <yhlu@tyan.com>
Nvidia Ck804 support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Hamish Guthrie <hamish@prodigi.ch>
Added NSC pc97317 super-io and added fill character option to config/Options.lb to speed up flash programming
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Hamish Guthrie <hamish@prodigi.ch>
Adds a tree for the Eaglelion mainboard. This board has an AMD GX1 processor in a typical Mini-ATX format with a few ISA and PCI slots.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1941 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Yinghai Lu <yhlu@tyan.com>
AMD MB IDE enable in Config.lb
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1940 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Ronald G. Minnich <rminnich@lanl.gov>
add in stepan's raminit code for the sc520
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1939 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Ronald G. Minnich <rminnich@lanl.gov>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1938 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Ronald G. Minnich <rminnich@lanl.gov>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1935 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Ronald G. Minnich <rminnich@lanl.gov>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1933 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Ronald G. Minnich <rminnich@lanl.gov>
add console options to via/epia/Options.lb
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1932 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Yinghai Lu <yhlu@tyan.com>
rm tyan VERSION
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1928 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Yinghai Lu <yhlu@tyan.com>
ide_enable in MB Config and jmp_auto ( it will make start in the 64k boundary)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1926 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Stefan Reinauer <stepan@openbios.org>
fix dram initialization on island/aruma
Never trust the specs. :-) I messed the different
cpu numbering notations up before. This makes my
wrong 8x patch obsolete as well.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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* create vital ACPI information from the linuxbios device tree.
* pass linuxbios information into dsdt.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1911 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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fixes to emulator.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1806 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- The sandpointx3+altimus has been consolidated into one directory for now.
- Added support for having different versions of the pci access functions
on a per bus basis if needed.
Hopefully I have not broken something inadvertently.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- optimize_link_read_pointers compiles now on the solo so don't disable it.
- Start sorting out the confusion between and object and an initobject on the ppc ports
- Major bugfix release of romcc to support to remove preprocessor deficiencies.
The line and column numbers are computed are now correct. But watch out
the error messages sometimes report the location of the next token so things
are still a little skewed.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1781 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Set adl855pc ROM_SIZE to 1M
Other minor debug prints until we get this fixed.
We're almost as far along as we were before the Change :-)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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complex expression.
crt0.S.lb: Modified so that it is safe to include console.inc
console.c: Added print_debug_ and frieds which are non inline variants of the normal console functions
div64.h: Only include limits.h if ULONG_MAX is not defined and define ULONG_MAX on ppc
socket_754/Config.lb Conditionally set config chip.h
socket_940.c We don't need and #if CONFIG_CHIP_NAME we won't be linked in if there are no references.
slot_2/chip.h: The operations struct need to be spelled cpu_intelt_slot_2_ops
slot_2/slot2.c: The same spelling fix
socket_mPGA603/chip.h: again
socket_mPGA603/socket_mPGA603_400Mhz.c: and again
socket_mPGA604_533Mhz/Config.lb: Conditionally defing CONFIG_CHIP_NAME
socket_mPGA604_800Mhz/chip.h: Another spelling fix
socket_mPGA604_800Mhz.c and again
via/model_centaur/model_centaur_init.c: It's not an intel CPU so don't worry about Intel microcode uptdates
earlymtrr.c: Remove work around for older versions of romcc
pci_ids.h: More ids.
malloc.c: We don't need string.h any longer
uart8250.c: Be consistent when delcaring functions static inline
arima/hdama/mptable.c: Cleanup to be a little more consistent
amdk8/coherent_ht.c:
- Talk about nodes not cpus (In preparation for dual cores)
- Remove clear_temp_row (as it is no longer needed)
- Demoted the failure messages to spew.
- Modified to gracefully handle failure (It should work now if cpus are removed)
- Handle the non-SMP case in verify_mp_capabilities
- Add clear_dead_routes which replaces clear_temp_row and does more
- Reorganize setup_coherent_ht_domain to cleanly handle failure.
- incoherent_ht.c: Clean up the indenation a little.
i8259.c: remove blank lines at the start of the file.
keyboard.c: Make pc_keyboard_init static
ramtest.c: Add a print out limiter, and cleanup the printout a little.
amd8111/Config.lb: Mention amd8111_smbus.c
amd8111_usb.c: Call the structure usb_ops not smbus_ops.
NSC/pc97307/chip.h: Fix spelling issue
pc97307/superio.c: Use &ops no &pnp_ops.
w83627hf/suerio.c: ditto
w83627thf/suerio.c: ditto
buildrom.c: Use braces around the body of a for loop. It's more maintainable.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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The static device tree is not built properly at all yet, but at least we get through it.
FIXME (What is the proper way to handle add in boards?)
- Add generic div64 support and ppc div64 support
- Fix abuild so it properly generates the CC line when cross compiling.
- Add one more possible ppc cross compiler target
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1762 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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CROSS_COMPILE
CC
HOSTCC
OBJCOPY
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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chip for the amdk8/root_complex
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1748 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1744 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1742 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1741 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1738 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Move pci_set_method out of hardwaremain.c
- Re-add debugging name field but only include the CONFIG_CHIP_NAME is
enabled. All instances are now wrapped in CHIP_NAME
- Many minor cleanups so most ports build.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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