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(Patch 2, refs #14)
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
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Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2527 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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and leaving enough room for a real payload (not /dev/null)
This is a wonderful example why "uses" sucks.
* add Config-abuild.lb for those boards that dont build with
the default settings and a real payload:
arima/hdama, amd/quartet, amd/serengeti_cheetah, ibm/e326
* if lzma is installed and a real payload is used, try compressing
it.
* fix a small bug in "abuild --help"
This patch is acked by me because its due to infrastructural changes only.
Flames welcome.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
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same format for all CHIP_NAME() entries in LinuxBIOS (Closes #20).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@linuxbios.org>
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
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and (hopefully) the correct canonical name of the vendor and board.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
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https://openbios.org/roundup/linuxbios/issue44
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48
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1201_ht_bus0_dev0_fidvid_mb.diff part 1
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NOTE: This will break the tree so it can be fixed up later
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1. x86_setup_mtrr take address bit.
2. generic ht, pcix, pcie beidge...
3. scan bus and reset_bus
4. ht read ctrl to decide if the ht chain
is ready
5. Intel e7520 and e7525 support
6. new ich5r support
7. intel sb 6300 support.
yhlu patch
1. split x86_setup_mtrrs to fixed and var
2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource
3. in_conherent.c K8_SCAN_PCI_BUS
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Creator: Yinghai Lu <yhlu@tyan.com>
add eswar code in intel car to disable Hyperthreading
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Creator: Yinghai Lu <yhlu@tyan.com>
write_pirq_routing_table for x86
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1979 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Creator: Li-Ta Lo <ollie@lanl.gov>
S4880 mainboard Config.lb
Comment in the Config.lb shoud be '#' rather than the C++ '//'.
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Creator: Yinghai Lu <yhlu@tyan.com>
remove junk in s2885 cache_as_ram_auto.c
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Creator: Yinghai Lu <yhlu@tyan.com>
intel car to x86 car
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Creator: Yinghai Lu <yhlu@tyan.com>
more safe stack in ram for cache_as_ram
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Creator: Yinghai Lu <yhlu@tyan.com>
cache_as_ram for AMD and some intel
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Creator: Yinghai Lu <yhlu@tyan.com>
s2881 dual core config
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Creator: Yinghai Lu <yhlu@tyan.com>
AMD D0/E0 Opteron new mem mapping support, AMD E Opteron mem hole support,AMD K8 Four Ranks DIMM support
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Creator: Yinghai Lu <yhlu@tyan.com>
remove lsi/53c1030 in MB Config
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Creator: Yinghai Lu <yhlu@tyan.com>
Nvidia Ck804 support
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Creator: Yinghai Lu <yhlu@tyan.com>
rm tyan VERSION
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Creator: Yinghai Lu <yhlu@tyan.com>
ide_enable in MB Config and jmp_auto ( it will make start in the 64k boundary)
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CROSS_COMPILE
CC
HOSTCC
OBJCOPY
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chip for the amdk8/root_complex
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- Move pci_set_method out of hardwaremain.c
- Re-add debugging name field but only include the CONFIG_CHIP_NAME is
enabled. All instances are now wrapped in CHIP_NAME
- Many minor cleanups so most ports build.
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the time source. The apic timer also has a variable time base.
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- Rename chip_config chip_operations throughout the tree
- Fix Config.lb on most of the Opteron Ports
- Fix the amd 8000 chipset support for setting the subsystem vendor and device ids
- Add detection of devices that are on the motherboard (i.e. In Config.lb)
- Baby step in getting the resource limit handling correct, Ignore fixed resources
- Only call enable_childrens_resources on devices we know will have children
For some busses like i2c it is non-sense and we don't want it.
- Set the resource limits for pnp devices resources.
- Improve the resource size detection for pnp devices.
- Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels
- Added a header file to hold the prototype of isa_dma_init
- Fixed most of the superio chips so the should work now, the via superio pci device is the exception.
- The code compiles and runs so it is time for me to go to bed.
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Things are close but not quite there yet.
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Although it is not used currently, misuse of terminolog is still a misuse.
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cleanups. Drop "driver" code from mainboard directories and use them from the
driver directory instead
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