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2022-08-16mb/**/dsdt.asl: Drop misleading "OEM revision" commentAngel Pons
It is highly unlikely that the "OEM revision" of the DSDT is 0x20110725 on mainboards with a chipset not yet released on 2011-07-25. Since this comment is most likely to have been copy-pasted from other boards, drop it from boards which use a chipset newer than Sandy/Ivy Bridge. Change-Id: If2f61d09082806b461878a76b286204ae56bf0eb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-08-02mb/system76: Change touchpad detection methodTim Crawford
Use the new "detect" method instead of "probed". Fixes an uncommon issue where i2c-hid fails to initialize the device on Linux. Tested on: gaze15, gaze16-3060, lemp10, oryp8 Tested: - Linux: Touchpad works across 50 reboots - Windows: Touchpad is still detected as an I2C HID device - Windows: Extra I2C HID devices are not shown in Device Manager Change-Id: I6a899c64a6d77b65a2ae57ab8df81cd84b568184 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-07-23soc/intel/cannonlake: Set MAX_CPUS based on the SoC and PCHFelix Singer
Set the default value for MAX_CPUS in the SoC config and drop it from the mainboards where it is set to those values. Change-Id: Ib56fdcfe770ef736a2c5e183481d9f9966570e6d Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-16ec/system76/ec: Provide charging thresholds by defaultTim Crawford
Battery charging thresholds are a firmware implementation and not dependent on any hardware. It is expected that all boards using System76 EC firmware will select this option, so enable it by default. Leave it disabled on clevo/cml-u, which didn't have it selected. Change-Id: Id99d36eaf055a76b9e1eb732174017651de299a5 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-04-21tpm: Refactor TPM Kconfig dimensionsJes B. Klinke
Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-22mb/system76/lemp9: Make GPIO for touchpad interrupt level triggeredJeremy Soller
Fixes commit 6bcaf6f (mb/system76/lemp9: Configure IRQs as level triggered for HID over I2C), which changed the interrupt configuration in the device tree but not in the GPIO definitions. Tested on a System76 Lemur Pro (lemp9), multi-touch I2C-HID was working. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I7f0559675a65453a1ad071f96049549a2dc21378 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-01-21mb/system76/*: Enable measured bootTim Crawford
Tested by checking PCR-2 data is recorded in cbmem log. Change-Id: I70cb9a93de44e75f3a3ed24979c243fccea1213d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-23mb: Remove dot from end of non-sentence commentPaul Menzel
Run the command below to fix all occurrences. $ git grep -l 'configuration in bootblock\. \*/' | xargs sed -i 's,configuration in bootblock\. \*/,configuration in bootblock */,' Change-Id: I84669341e2c8976953284dbaf113da3397857de3 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-19mainboard: Fix comment about early GPIOsAngel Pons
These boards program the early GPIO table in bootblock, not romstage. Change-Id: Iae9353d106483f30cefa2d035d96e63e4c127261 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Sean Rhodes <admin@starlabs.systems> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-11-23mb/system76/*: Disable IME by CMOS optionTim Crawford
Add CMOS option to set IME mode. Default to "Disable" for CNL and TGL-H, and "Enable" for TGL-U. Not set for KBL, which uses ME_CLEANER. The HECI device must be enabled in devicetree for switching modes to function correctly. Change-Id: I3163dcb0a4af020c2cf6f94f2bb26380f17c253e Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-11-04mb/system76/*: Enable HECI deviceTim Crawford
The HECI device needs to be enabled to send the commands to have the CSME change between Soft Temporary Disable mode and Normal mode. Change-Id: I668507e3b522137bcc827aa615dab1fccd1709a0 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-11-02mb/system76/*: CMOS: Drop power_on_after_fail optionTim Crawford
Our boards do not boot if power_on_after_fail=Disable. Drop the option and use the default of powering on. Change-Id: Ia1857e52f838337048f79f8ca5c12d669cae321a Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-10-15mainboard: Drop invalid `VGA_BIOS_FILE` defaultsAngel Pons
If the VGA BIOS file path for `VGA_BIOS_FILE` in a mainboard's Kconfig does not exist in the coreboot tree (including submodules), drop it. These files should be stored in the `site-local` subdirectory and the paths specified for each board in `site-local/Kconfig`. For example: config VGA_BIOS_FILE default "site-local/x200_vbios.bin" if BOARD_LENOVO_X200 Note that this is just an example. There are better ways to structure one's `site-local` subfolder. Using the `CONFIG_MAINBOARD_DIR` option would be one of them, though variants may still need special handling. Also, update autoport to not generate `VGA_BIOS_FILE` defaults. Change-Id: I1b5dfba035a42d7943f270f95fb7d32b285584d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-09-10cannonlake mainboards: Set PMC as hidden in devicetreeTim Wawrzynczak
FSP-S hides the PMC from the PCI bus when it runs, but there are still initialization steps coreboot programs for the PMC. Therefore, change all of the cannonlake mainboards to set the PMC as hidden in the devicetree, which means the device will be skipped during enumeration, but device callbacks are still issued as if the device were enabled. TEST=Ran full patch train on google/dratini, disassembled SSDT and the PEPD device matches what is in pep.asl. Also verified via dmesg that the INT33A1 device is still initialized by the kernel. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib4a20ce9075ce7653388a5d3e281fe774bf89355 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-03src/*: Specify type of `DIMM_MAX` onceAngel Pons
Specify the type of the `DIMM_MAX` Kconfig symbol once. Change-Id: I2e86baaa8bd50c7b82c399fde5dcea05da6b4307 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-09-02mb/system76/*: cmos.layout: Reserve century byteTim Crawford
Windows will write to the century byte (0x32), causing the option table checksum to be invalid and reset all options to their default values. Move options and checksum to start after the century byte. Change-Id: Ia395acacda1e251251c880587bbf61d7ee81ba3d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-08-28soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by defaultFelix Singer
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the default by changing its enum value to 0 and remove its configuration from all related devicetrees. If `common_soc_config.chipset_lockdown` is not configured with something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT` is used. Also, add a release note for the upcoming 4.15 release. Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-12mb/system76/*: Add CMOS option tableTim Crawford
System76 uses several custom CMOS values downstream. Reduce our diff by providing a generic layout with the defaults: boot_option=Fallback debug_level=Debug power_on_after_fail=Enable Tested on galp3-c, gaze15, oryp5, oryp6. All boards boot multiple times with USE_OPTION_TABLE selected. Change-Id: Ie57b0e5713bba8ad46e1a4123a3ddd43e0eea964 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-07-26mb/*: Specify type of `MAINBOARD_PART_NUMBER` onceAngel Pons
Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_DIR` onceAngel Pons
Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26src/*: Specify type of `CBFS_SIZE` onceAngel Pons
There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol more than once. This is done in `src/Kconfig`, along with its prompt. Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-22soc/intel/cannonlake: Set DIMM_SPD_SIZE to 512Felix Singer
All related mainboards are setting DIMM_SPD_SIZE to 512. Therefore, default to 512 in the SoC Kconfig and drop it from related mainboard Kconfigs. Change-Id: Idb6a0e42961eeb490afd76b4aa7d940961991733 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52513 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18soc/intel/cnl and mainboards: Drop `cnl_configure_pads()`Furquan Shaikh
CB:31250 ("soc/intel/cannonlake: Configure GPIOs again after FSP-S is done") introduced a workaround in coreboot for `soc/intel/cannonlake` platforms to save and restore GPIO configuration performed by mainboard across call to FSP Silicon Init (FSP-S). This workaround was required because FSP-S was configuring GPIOs differently than mainboard resulting in boot and runtime issues because of misconfigured GPIOs. This issue has since been fixed in FSP (verified with FSP v1263 on hatch). However, there were still 4 boards in coreboot using `cnl_configure_pads()`. As part of RFC CB:50829, librem_cnl, clevo/cml-u and system76/lemp9 were tested to ensure that this workaround is no longer required. This change drops the workaround using `cnl_configure_pads()` and updates all mainboards to use `gpio_configure_pads()` instead. Signed-off-by: Furquan Shaikh <furquan@google.com> Tested-by: Angel Pons <th3fanbus@gmail.com> (Tested purism/librem_cnl) Tested-by: Michael Niewöhner <foss@mniewoehner.de> (Tested clevo/cml-u which is similar to system76/lemp9) Change-Id: I7a4facbf23fc81707cb111859600e641fde34fc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52248 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16mb/system76/lemp9: correct pad GPP_A11 (INTP_OUT)Michael Niewöhner
This pad is connected to INTP_OUT of the Type-C PD controller. Correct the comment. Also remove the unneeded pull-up. Checked with schematics. Change-Id: I16a769ac6a2d54da700ddb45bd9c7c84383a43dd Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2021-04-12mb/*: drop LPC generic range for port 80Michael Niewöhner
Port 80 (actually 0x80-0x8f) is a fixed I/O range and thus does not have to be set up as generic range. Drop the entries from the devicetrees. Change-Id: I8a54d3c35a321a2d57bd846662f7339eff53e5a8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-08soc/intel/{cannonlake,icelake}: Drop unhooked `SendVrMbxCmd`Angel Pons
This option's value is not used anywhere. Remove it. Change-Id: I0f30cddd30d459f48b51f377b111bbc04709c5f8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-06mb/system76: acpi: Remove unused EC defineTim Crawford
The define for color keyboard setting has never been used, as it was added as a Kconfig selection when ec/system76/ec was introduced. Change-Id: Ib83d4510c14ddf083660e42175ab093403792cac Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-03-19mb/{clevo/cml-u,system76/lemp9}: Clarify `gen2_dec` useAngel Pons
This I/O range is for a PM channel on the EC, not the PCH PMC. Change-Id: I64422e537c1edcd0673cf87f16139fb117b10e75 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51604 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-11mb/system76/lemp9: Drop unneeded memcfg values and commentsAngel Pons
This mainboard uses a Comet Lake SoC and mixed-topology DDR4 memory. Drop LPDDR-specific DQ and DQS mappings and comment about Cannon Lake. Change-Id: Icb986d1c074e64b3cfad3897b69d35d108f64bff Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-12mb/system76/lemp9: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Ice096777077bd2e9cfbaf744371fc372c0c05606 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-27ACPI: Add top-level ASLKyösti Mälkki
Objects that are created with acpigen need to be declared with External () for the generation of dsdt.asl to pass iasl without errors. There are some objects that are common to all platforms, and some that should be declared only conditionally. Having a top-level ASL helps to achieve this. Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-16mb/system76/lemp9: do early pad configuration in early bootstageMichael Niewöhner
Do early pad configuration in early bootblock before console init, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: Ie122a441145383b820d96e32ce1581dfc27fa57b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2020-12-17soc/intel/cannonlake: Change mainboard_silicon_init_params argumentPatrick Rudolph
Use FSPS_UPD instead of FSP_S_CONFIG as argument as already done on xeon_sp and denverton_ns. This allows to set test config UPDs from mainboard code as well. Change-Id: I6d67264e22df32b9210ce88b99d6a7a4f6b97ffb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-12-08mb/*: Remove SATA mode config for CNL based mainboardsFelix Singer
SATA_AHCI is already the default mode for CNL based mainboards. Therefore, remove its configuration from all related devicetrees. Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I814e191243224a4b021cd7d4c1b611316f1fd1a4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-08soc/intel/cannonlake: Align SATA mode names with soc/sklFelix Singer
Align the SATA mode names with soc/skl providing a consistent API. Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I54b48462852d7fe0230dde0c272da3d12365d987 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-06mb/*: Remove unnecessary selectsFelix Singer
Remove SOC_INTEL_COMMON_BLOCK_HDA from mainboards Kconfig since it is selected by their SoC soc/intel/cannonlake. Change-Id: I9597746a217575b42f6325998b948e16b452231a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48289 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02mb/system76/lemp9: Enable battery charging thresholdsTim Crawford
Change-Id: I5131cf350d5b8c2a45f8d8245c0df26742c0d732 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45533 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02mb, soc/intel: Reorganize CNVi device entries in devicetreeFurquan Shaikh
This change reorganizes the CNVi device entries in mainboard devicetree/overridetree and SoC chipset tree to make it consistent with how other SoC internal PCI devices are represented i.e. without a chip driver around the SoC controller itself. Before: chip drivers/wifi/generic register "wake" = "..." device pci xx.y on end end After: device pci xx.y on chip drivers/wifi/generic register "wake" = "..." device generic 0 on end end end Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-10-26mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`Michael Niewöhner
The dt option `speed_shift_enable` is obsolete now. Drop it. Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-10-13{src/mb,util/autoport}: Use macro for DSDT revisionElyes HAOUAS
Change-Id: I5a5f4e7067948c5cc7a715a08f7a5a3e9b391191 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-10-13mb, soc/intel: Switch to using drivers/wifi/generic for Intel WiFi devicesFurquan Shaikh
This change switches all mainboard devices to use drivers/wifi/generic instead of drivers/intel/wifi chip driver for Intel WiFi devices. There is no need for two separate chip drivers in coreboot to handle Intel and non-Intel WiFi devices since the differences can be handled at runtime using the PCI vendor ID. This also allows mainboard to easily multi-source WiFi chips and still use the same firmware image without having to distinguish between the chip drivers. BUG=b:169802515 BRANCH=zork Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-05soc/intel/common/block/acpi: Factor out common platform.aslSubrata Banik
This patch moves platform.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CNL and CML platform. 1) Dump and disassemble DSDT, verify _PIC method present inside common platform.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I5189b03d6abfaec39882d28b40a9bfa002128be3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-23treewide: rename GENERIC_SPD_BIN to HAVE_SPD_BIN_IN_CBFSMichael Niewöhner
The name GENERIC_SPD_BIN doesn't reflect anymore what that config is used for, so rename it to HAVE_SPD_BIN_IN_CBFS. Change-Id: I4004c48da205949e05101039abd4cf32666787df Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45147 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-22mb/system76/lemp9: gpio: convert gpio.h to a cleaner formatMichael Niewöhner
Convert gpio.h to a compacter, cleaner format by keeping gpios in a single line, where possible. This was done with the following fancy vim regex replacement commands. (Neither sed, nor awk multiline matching syntax are friends with me...) Just open src/mainboard/system76/lemp9/gpio.h with vim, type : before pasting each command, press enter and see how the format changes. g#^\t//#d %s/^\t\t/\t/ g/PAD_.*$\n\n[^/]/s/\n// g#// NC#d %s#^\t// \(.*\)\n\t// \(.*\)#\t// \1 \2#g %s#^\t// \(.*\)\n\t\(PAD_.*,\)#\t\2\t\t/* \1 */ %s#^// \(GP.*\)#\t/* ------- GPIO Group \1 ------- */# Finally some indents and multiline comments need to be fixed manually. Test: images built with TIMELESS do not differ. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I9054274dc4c8942935b6a4789bfc1547dd3d4017 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-09-22mb/system76/lemp9: convert inverted SCI/SMI macros to _LOW macroMichael Niewöhner
Convert PAD_CFG_GPI_S*I(..., INVERT) to PAD_CFG_GPI_S*I_LOW(...), which is better understandable. Change-Id: I147c82d738623bff54122ad5ef8ece028c562cab Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45488 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21mb/system76/lemp9: gpio: convert the remaining raw pads to macrosMichael Niewöhner
Convert the EC and touchpad interrupt pads from raw to macros. This was done with intelp2m. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I79d2cca0f300e6daf1c1923a1882e4cc1ffc3c8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/43648 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-20mb/system76/lemp9: move LPC options to the devicetreeMichael Niewöhner
Change-Id: I7b7acdc51c848541fb39926bc8de1115c026dd05 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45496 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-20mb/system76/lemp9: correct CBFS_SIZEMichael Niewöhner
The BIOS region size is 0xc00000, not 0xa00000. Correct this. Change-Id: I88cb0d4b9a590a32672054aa0db7f9a92070ff6d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-09-20mb/system76/lemp9: enable SATA ALPM capabilityMichael Niewöhner
Enable SATA Link Power Management capability to be able to save power. TEST: /sys/class/scsi_host/host*/link_power_management_policy exists. Change-Id: I88de28cfb266af3fcd6e498a08a24b46c992cb9d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45492 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-20mb/system76/lemp9: drop disabled options from devicetreeMichael Niewöhner
Drop all options with zero-value, since they already default to 0. Change-Id: I2a1a91778e83dc49c6dcf2d518cd3591f7ec4cfa Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45491 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-19mb/system76/lemp9: move subsystem id from Kconfig to devicetreeMichael Niewöhner
Change-Id: I21e7e53787b115f50093d7caa72285ce480cef52 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-17mb/system76/lemp9: update power limitsJeremy Soller
Tested on lemp9, power limits are adjusted from the previously low values to the values the thermal system can handle. This was determined by increasing the values and running the system at 100% CPU utilization until thermal throttling occured and the chassis temperature became uncomfortable. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I5e176e9d98376f8e2dc415e4397efc456869e72d Reviewed-on: https://review.coreboot.org/c/coreboot/+/43624 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17mb/system76/lemp9: disable PCH DMIC, which is not wiredMichael Niewöhner
The microphone is wired to the audio codec, not to the PCH. Disable the DMIC interface. Change-Id: I4128a694c1a66d3c2c2d1cb831fcca3487160f8f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45133 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17mb/system76/lemp9: skip FSP init of UART2Jeremy Soller
This UART is already initialized by coreboot for the console, it does not need to be initialized by the FSP. Tested on lemp9. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I7c299fd7cf6fe53d1f500a899a14e63e51ad6266 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-17mb/system76/lemp9: move HDA options into devicetreeMichael Niewöhner
Change-Id: Id4fc12896f89739d0ee2a47a42173693921da14e Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45132 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08mb/system76/lemp9: update HDA pin configJeremy Soller
To minimize the quirks the kernel has to apply, the headset mic is set to its correct value in coreboot. Tested on lemp9, audio is functional. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I6b59de95f01360a5f7779f87f39edeb75dedc215 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43631 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-07mb/system76/lemp9: Add SMBIOS descriptions to root portsFelix Singer
Change-Id: Ie663d424edbbeeb8f5691b00f3977f7501e9ab45 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-07mb/system76/lemp9: Move PCIe root port config into devicetreeFelix Singer
Change-Id: Idd38ab530fd8a0c16231f3499eac393c333a9a92 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-07mb/system76/lemp9: Add comments to SATA portsFelix Singer
Change-Id: I8db3bfbdb557a84413408b4b39a13b24c45497cc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-07mb/system76/lemp9: Move USB options into devicetreeFelix Singer
Change-Id: I3371bed7c2678fbc3304f53af1413a93462933f5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-07mb/system76/lemp9: Enable SataPortsDevSlpFelix Singer
Enable SataPortsDevSlp for SATA ports 2 and 3. Change-Id: Id6c69f4a6fe45cb5c6aad3f42c741a2724c6166c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-07mb/system76/lemp9: Move SATA options into devicetreeFelix Singer
Change-Id: Idf64d98b36ca95a8bc17a6544993c26e23851cd8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-07mb/system76/lemp9: Don't configure unused SATA / USB portsFelix Singer
Change-Id: Ic5587402700d7b137e20538549b8a09a64cb6a9f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-06mb/system76/lemp9: enable I2C HID touchpadJeremy Soller
Enable the I2C HID driver, configure I2C bus 0 and add the touchpad device to the devicetree. Tested on lemp9, touchpad confirmed to use i2c-hid driver in Linux instead of PS/2. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: Ic3a90fda134b1d53f28ab687b3033ec52fee843b Reviewed-on: https://review.coreboot.org/c/coreboot/+/43623 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-06mb/system76/lemp9: Use absolute path for _GPEJeremy Soller
_GPE cannot be anywhere but at the root of the ACPI namespace. This change ensures that is always the case. Tested on lemp9, GPE still in correct location. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: Ib31683b06e61da4b1859cd939c36879cebf4c03c Reviewed-on: https://review.coreboot.org/c/coreboot/+/43630 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-06mb/system76/lemp9: Drop DeepSx settingsJeremy Soller
The GPIOs required for DeepSx (e.g. SLP_SUS#) are not hooked up on the lemp9. Therefore, drop the DeepSx settings. Tested on lemp9, suspend works correctly. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: Iab179abd7adc3a65dcfc43ce1b5742d514b711fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/43629 Reviewed-by: Michael Niewöhner Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-06mb/system76/lemp9: Enable SA thermal deviceJeremy Soller
Tested on lemp9, SA thermal device appears in lspci. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I527e586b1dae5f8087d2364c63c9db5bcb643214 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner
2020-09-05mb/system76/lemp9: Don't enable unused USB3 portFelix Singer
Don't configure USB3 port 4 since it's not used. Change-Id: I6919f5ec3a5be53373f2ab75063764287b53baf5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Michael Niewöhner
2020-09-04soc/intel/cnl: Enable HECI3 depending on devicetreeFelix Singer
Currently HECI3 gets enabled by the option Heci3Enabled, but this duplicates the devicetree on/off options. Therefore depend on the devicetree for enablement of the HECI3 controller. All corresponding mainboards were checked if the devicetree configuration matches the Heci3Enabled setting, and divergent devicetrees were adjusted. Change-Id: Ic7d52096aee225c2ced1e1bc29ca850fe5073edc Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44579 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-03soc/intel/cnl: Add new Kconfig option which matches its FSPs nameFelix Singer
Since there are 4 different versions of FSPs for the Comet Lake platform, add a new Kconfig option for the currently used SoC being able to differ between the various SoCs and FSPs. The new Kconfig option selects the Comet Lake SoC as base for taking over its specific configuration and is only used for configuring the path to its specific FSP header files and FSP binary. Also, adjust all related mainboards so that their Kconfig selects the new option. For details, please see https://github.com/intel/FSP/tree/master/CometLakeFspBinPkg Built System76/lemp9 with BUILD_TIMELESS=1 before and after this patch and both images are equal. Change-Id: I44b717bb942fbcd359c7a06ef1a0ef4306697f64 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-02mb/*/Kconfig: Drop redundant 'select DRIVERS_INTEL_WIFI'Elyes HAOUAS
DRIVERS_INTEL_WIFI is already set to yes. Change-Id: I09f628a9c1feb8992b6fe7c7ca93c75243ffc0f1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-02mb/*/Kconfig: Drop redundant 'select GENERATE_SMBIOS_TABLES'Elyes HAOUAS
GENERATE_SMBIOS_TABLES is already set to yes at src/Kconfig Change-Id: I2845f4f329283360a49ea40dfee7d9a232ab4ea1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-30mb/system76/lemp9: gpio: add a pull-down for MODEM_CLKREQ / CNVI_CLKREQMichael Niewöhner
MODEM_CLKREQ / CNVI_CLKREQ has no external pull-down resistor. When there is no M.2 card populated, the pin is floating. Thus enable an internal 20K PD. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I37e0a9d7e9e0a8c8a7ac198abfd3995b8b0f9e3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/43651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-08-30mb/system76/lemp9: add wifi devicesMichael Niewöhner
Add CNVi and PCIe wifi devices to the devicetree and enable the wifi driver and SMBIOS tables in Kconfig. Test: both CNVi and PCIe wifi devices work fine Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I16e04dbbf5fc3a163ce5a2bb8de646877d5cbc0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/43654 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30mb/system76/lemp9: gpio: rework commentsMichael Niewöhner
Rework the comments: - fix wrong gpio / net names - convert all comments to <gpio> / <net name> - add more information where appropriate Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I51b552fd3255d5627dcc012e677bad51be517cf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43650 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30mb/system76/lemp9: gpio: convert PAD_CFG_TERM_GPO to PAD_CFG_GPOMichael Niewöhner
Convert PAD_CFG_TERM_GPO with pull "NONE" to its shorter equivalent PAD_CFG_GPO. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I9ed4d97ba184fa3e72425d5d16042a142b0640b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43649 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30mb/system76/lemp9: gpio: disable unused pad for INTP_OUTMichael Niewöhner
INTP_OUT can be used as Type-C VBUS sense input/interrupt but is currently unused in coreboot. It isn't a requirement for PD to work. Disable it for now. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I233fbb562969487dff095ba6589fb9da3301ae4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/43647 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30mb/system76/lemp9: gpio: disable internal SATAXPCIE pull-upsMichael Niewöhner
Disable internal pull-ups for SATAXPCIE pads since there are external ones at the M.2 slot's PEDET pins. Test: both, SATA and NVME devices work fine on both slots Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I6be716620695ac38c44a17abe1c4de97b099b8d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43645 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30mb/system76/lemp9: gpio: configure unused padsMichael Niewöhner
There are pads being unused for various reasons: a) missing board support (DeepSx: SUSWARN#) b) unneeded feature ID pins - currently no known device models without keyboard backlight - currently no known device models without TPM c) BOARD_ID (L140CU/L140ZU) is fixed and known at build time d) DDR_TYPE_*: there is only one known ram model e) strap-only pads f) unconnected pads Configure them as NC with appropriate pull-up if no external pull exists. The latter was checked by schematics and looking at the board. When any of the unused ID pins is needed in the future, they can be reactivated easily (configure as GPI). Further, convert from use of legacy macro PAD_CFG_NC to PAD_NC. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Ia370c180d5ae6f48360be14af3cbab29e6814e75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43644 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30mb/system76/lemp9: enable TPMMichael Niewöhner
L140CU has a TPM2 connected via SPI. Add the TPM device to the devicetree and enable it. According to Intel doc#615170-001, PIRQ is required for SPI TPM to work. Since the TPM is connected to GPP_A7, enable NF1 (PIRQA#) and set it as TPM interrupt in Kconfig. Note: The PCH maps either LPC TPM or SPI TPM to the same address and handles either LPC or SPI communication transparently. Thus we can use MAINBOARD_HAS_LPC_TPM here, which implements TPM via that address. Tested, but only polling works currently, because there is some upstream issue with the tpm_tis module in current Linux kernels. [1] [1] https://bugzilla.redhat.com/show_bug.cgi?id=1770021 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I26d3b396fe1e99368e18fd3a6a9f02e3585b9f6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/43641 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-23soc/intel/cnl: Configure FSP option PcieRpSlotImplementedNico Huber
Allow configuring FSP option PcieRpSlotImplemented. Also, update all related devicetrees and configure PcieRpSlotImplemented to keep the current behaviour. Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-08-07soc/intel/cnl: Set Heci1Disable depending on devicetree configFelix Singer
Currently HECI1 gets enabled by the option HeciEnabled, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement/disablement of the HECI1 device. All corresponding mainboards were checked if the devicetree matches the HeciEnabled setting, and adjusted where necessary. Change-Id: I03dd3577fbe3f68b0abc2d196d016a4d26d88ce5 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-28mb/system76/lemp9: Relocate device enable optionsFelix Singer
Built with BUILD_TIMELESS=1, resulting coreboot.rom does not change. Change-Id: I655bc7576e8ff48258a2a19387e01372f4bbea3d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner
2020-07-23ec/system76_ec: add support for System76 ECJeremy Soller
This adds ACPI code for System76 EC and converts system76/lemp9 to use EC_SYSTEM76_EC. Tested on system76/lemp9. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I1f693268d94b693b6764e4a3baf4c3180689f3be Reviewed-on: https://review.coreboot.org/c/coreboot/+/43612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Michael Niewöhner
2020-07-21mb/system76/lemp9: drop FSP_M_XIPMichael Niewöhner
Drop FSP_M_XIP since it's selected by the soc already. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I999d369be395de08d4ab7f115fedf4b7fa10eb34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-07-21mb/system76/lemp9: drop ONBOARD_VGA_IS_PRIMARYMichael Niewöhner
Drop config ONBOARD_VGA_IS_PRIMARY as it's only needed for mainboards with multiple graphics devices. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I6525c65af3dcfc96ea3d68a1388432179e9ac43d Reviewed-on: https://review.coreboot.org/c/coreboot/+/43636 Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-19mb/*/*/Kconfig: guard board name in quotesPatrick Georgi
New kconfig dislikes unquoted slashes. Change-Id: Ief242de081071021b9c904a24535d025f6674270 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42480 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26cannonlake: update processor power limits configurationSumeet R Pawnikar
Update processor power limit configuration parameters based on common code base support for Intel Cannonlake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on drallion system Change-Id: Iac6e6f81343fcd769619e9d7ac339430966834f6 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-26intel/cannonlake: Implement PCIe RP devicetree updateNico Huber
Some existing devicetrees were manually adapted to anticipate root-port switching. Now, their PCI-device on/off settings should just reflect the `PcieRpEnable` state and configuration happens on the PCI function that was assigned at reset. Change-Id: I4d76f38c222b74053c6a2f80b492d4660ab4db6d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-15Do not select USE_BLOBSNico Huber
The `USE_BLOBS` config only exists for idealistic reasons. If we would allow us to use blobs by default, we wouldn't need that option and could just always do it. It's generally debatable for the project as a whole, but not per board/subject. Change-Id: I8591862699aef02e5a4ede32655fc82c44c97555 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-10src/mb: Remove unneeded spaces before/after tabsElyes HAOUAS
Change-Id: I02979a0632a7b356985f96c3ba239daba178b4e3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39989 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-05fsp2_0: Clean up around `config FSP_USE_REPO`Nico Huber
We can make our lifes much easier by removing its dependency on `ADD_FSP_BINARIES`. Instead, we imply the latter if the repository is to be used. We can also hide a lot of unnecessary prompts in this case. Also, remove default overrides and selects for the two that are now unnecessary. Change-Id: I8538f2e966adc9da0fbea2250c954d86e42dfeb3 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39882 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-04mainboard/system76: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I2aa745e03e62ff8b9b5c9cb6f91d7f832f599f8d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-18mainboard/[^a-p]*: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I18e513cefc373b1cd70d31d1159928cc948a8476 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-01-27mainboard/system76: Add System76 Lemur Pro (lemp9)Jeremy Soller
The System76 Lemur Pro (lemp9) is an upcoming laptop computer. Support in coreboot is developed by System76 and provided as the default firmware option. Testing is done on a pre-production model expected to be identical from a firmware perspective to the production model. Working: - Payload - Tianocore - CPU - Intel i7-10510U - Intel i5-10210U - EC - ITE IT5570E running https://github.com/system76/ec - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys - Battery - Charger, using AC adapter or USB-C PD - Suspend/resume - Touchpad - GPU - Intel UHD Graphics 620 - GOP driver is recommended, VBT is provided - eDP 14-inch 1920x1080 LCD - HDMI video - USB-C DisplayPort video - Memory - Channel 0: 8-GB on-board DDR4 Samsung K4AAG165WA-BCTD - Channel 1: 8-GB/16-GB/32-GB DDR4 SO-DIMM - Networking - M.2 PCIe/CNVi WiFi/Bluetooth - Sound - Realtek ALC293D - Internal speaker - Internal microphone - Combined headphone/microphone 3.5-mm jack - HDMI audio - USB-C DisplayPort audio - Storage - M.2 PCIe/SATA SSD-1 - M.2 PCIe/SATA SSD-2 - RTS5227S MicroSD card reader - USB - 1280x720 CCD camera - USB 3.1 Gen 2 Type-C (left) - USB 3.1 Gen 2 Type-A (left) - USB 3.1 Gen 1 Type-A (right) Not working: - TPM2 - SPI bus 0, chip select 2 is used. Chip selects other than 0 are not currently supported by the intel fast_spi driver. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: Ib0a32bbc6f89a662085ab4a254676bc1fad7dc60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 14:51:12 +0000