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Use the new "detect" method instead of "probed". Fixes an uncommon issue
where i2c-hid fails to initialize the device on Linux.
Tested on: gaze15, gaze16-3060, lemp10, oryp8
Tested:
- Linux: Touchpad works across 50 reboots
- Windows: Touchpad is still detected as an I2C HID device
- Windows: Extra I2C HID devices are not shown in Device Manager
Change-Id: I6a899c64a6d77b65a2ae57ab8df81cd84b568184
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Battery charging thresholds are a firmware implementation and not
dependent on any hardware. It is expected that all boards using System76
EC firmware will select this option, so enable it by default.
Leave it disabled on clevo/cml-u, which didn't have it selected.
Change-Id: Id99d36eaf055a76b9e1eb732174017651de299a5
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Add an enum for `DdiPortXConfig` devicetree options. Note that setting
these options to zero does not disable the corresponding DDI port, but
instead indicates that no LFP (Local Flat Panel, i.e. internal LCD) is
connected to it.
Change-Id: I9ea10141e51bf29ea44199dcd1b55b63ec771c0a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
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Break TPM related Kconfig into the following dimensions:
TPM transport support:
config CRB_TPM
config I2C_TPM
config SPI_TPM
config MEMORY_MAPPED_TPM (new)
TPM brand, not defining any of these is valid, and result in "generic" support:
config TPM_ATMEL (new)
config TPM_GOOGLE (new)
config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE)
config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE)
What protocol the TPM chip supports:
config MAINBOARD_HAS_TPM1
config MAINBOARD_HAS_TPM2
What the user chooses to compile (restricted by the above):
config NO_TPM
config TPM1
config TPM2
The following Kconfigs will be replaced as indicated:
config TPM_CR50 -> TPM_GOOGLE
config MAINBOARD_HAS_CRB_TPM -> CRB_TPM
config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL
config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE
config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL
config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM
config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL
config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE
Signed-off-by: Jes B. Klinke <jbk@chromium.org>
Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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All TGL mainboards are setting DIMM_SPD_SIZE to 512. Thus, default to
512 in the SoC Kconfig and drop it from the mainboard Kconfigs.
Change-Id: I9fd947b61c984e10bd5fba20b73280b08623a008
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62766
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch modifies `memcfg_init` and `variant_memory_init`functions
argument from FSP_M_CONFIG to FSPM_UPD.
This change in `memcfg_init()` argument will help to update the
architectural FSP-M UPDs from common code blocks rather than going
into SoC and/or mainboard implementation.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=Able to build and boot redrix without any visible failure/errors.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
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This reverts commit bd9b044a96cc ("mb/system76: rtd3: Remove SrcClk pin
on CPU RP").
Previously, RTD3 expected a PCH index for the root port and did not work
with the CPU PCIe RP present on TGL, so SrcClk pin was disabled.
Set them now that RTD3 supports mapping the index for the CPU RP.
Change-Id: Ia7519b9f5a2be52cd5575615c28d20371a26996b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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Tested by checking PCR-2 data is recorded in cbmem log.
Change-Id: I70cb9a93de44e75f3a3ed24979c243fccea1213d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4a81fd58df468e2711108a3243bf116e02986316
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI
bit set for any slots of already existing boards, add set the option
PcieRpSlotImplemented=1 where appropriate.
Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Hook up `Device4Enable` FSP setting to devicetree state and drop its
redundant devicetree setting `Device4Enable`.
The following mainboards enable the DPTF device in the devicetree
despite `Device4Enable` is not being set.
* google/deltaur
Thus, set it to off to keep the current state unchanged.
Change-Id: Ic7636fc4f63d4beab92e742a6882ac55af2565bc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Hook up `SmbusEnable` FSP setting to devicetree state and drop its
redundant devicetree setting `SmbusEnable`.
The following mainboards enable the SMBus device in the devicetree
despite `SmbusEnable` is not being set.
* google/deltaur
* starlabs/laptop
Thus, set it to off to keep the current state unchanged.
Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Select the EC option on boards with dGPUs to report GPU temperature and
fan data.
Tested on system76/oryp6. The GPU fan speed is reported in sensors when
the system is under load.
system76_acpi-acpi-0
Adapter: ACPI interface
CPU fan: 1985 RPM
GPU fan: 2348 RPM
CPU temp: +68.0°C
GPU temp: +0.0°C
Change-Id: Ieb45dc277c7eb11be1c50b9a9e3e20e3a88578b7
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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Add CMOS option to set IME mode. Default to "Disable" for CNL and TGL-H,
and "Enable" for TGL-U. Not set for KBL, which uses ME_CLEANER.
The HECI device must be enabled in devicetree for switching modes to
function correctly.
Change-Id: I3163dcb0a4af020c2cf6f94f2bb26380f17c253e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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https://tech-docs.system76.com/models/gaze16/README.html
The gaze16 comes in 3 variants due to differences in the discrete GPU
and network controller used.
- NVIDIA RTX 3050, using Realtek Ethernet controller
- NVIDIA RTX 3060, using Realtek Ethernet controller
- NVIDIA RTX 3060, using onboard Intel I219-V Ethernet controller
Tested on the 3050 variant.
Tested with TianoCore (UefiPayloadPkg).
Working:
- PS/2 keyboard, touchpad
- Both DIMM slots
- M.2 NVMe SSD
- M.2 SATA SSD
- 2.5" SSD
- All USB ports
- SD card reader
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- HDMI output
- Internal microphone
- Internal speakers
- Combined headphone + mic 3.5mm audio*
- 3.5mm microphone input*
- S3 suspend/resume
- Booting to Pop!_OS Linux 21.04 and Windows 10 20H2
- Flashing with flashrom
Not working:
- Discrete/Hybrid graphics
- Mini DisplayPort output (requires NVIDIA GPU)
- 3.5mm audio input/output detection on Windows
Change-Id: Ifb90f9b73a10abf53a21738e2c466d539df9a37c
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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