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2013-08-15Include boot_cpu.c for romstage buildsKyösti Mälkki
ROMCC boards were left unmodified. Change-Id: I3d842196b3f5b6999b6891b914036e9ffcc3cef0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3853 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-07-10Rename hardwaremain() to main()Stefan Reinauer
... and drop the wrapper on ARMv7 Change-Id: If3ffe953cee9e61d4dcbb38f4e5e2ca74b628ccc Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3639 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-04intel/i5000: Use MMCONF_SUPPORT_DEFAULTKyösti Mälkki
Change all PCI configuration accesses to MMIO on two boards with i5000 chipset. To enable MMIO style access, add explicit PCI IO config write in the bootblock. Change-Id: I26f1c2da5ae98aeeda78bdcae0fb1e8c711a3586 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3601 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-03Move select MMCONF_SUPPORT under northbridgeKyösti Mälkki
Move/remove MMCONF_SUPPORT reference under mainboard Kconfig, as that feature originates from northbridge and cannot be disabled for a single mainboard. Change-Id: I6d6861079876ddddaff90b10f18edb6936e93bd0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3589 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-28Drop WARNINGS_ARE_ERRORS exceptionsStefan Reinauer
Thanks to Bruce's great work, we can finally drop this workaround. Change-Id: Ie92d1e53ef867fa34aa2489ccfb682d73195b213 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3569 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-28Supermicro H8SCM/H8QGI: Increase size of bus variable to meet APIBruce Griffith
Users of mptable_write_buses() pass two pass-by-reference parameters reflecting a maximum bus number and a search bus number. These bus numbers are expected to be held in "int" variables and are updated by the function. Both of the Supermicro boards define the search bus number as a byte value in mptable.c. For now, change the two Supermicro boards to use "int" to hold the search bus index. Change-Id: Ie71850719c1fa3cda0ac9c8773bb80650de95c70 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3546 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28AMD SB700 boards: Set Azalia configuration flagsBruce Griffith
The existing code for setting Azalia configuration assumes that the configuration bits are contiguous within a single byte and can be set using a byte copy addressed into the lowest 2-bit subfield. The fix in Family 14 defines a union that can be addressed as a byte to overlay the bit fields. Since the offset of the four subfields is not necessarily fixed, change the code to initialize each of the four subfields individually. Change-Id: I1dff20bb8bd3e1bcd8b4e6b0537e20779d2a3521 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3544 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28supermicro/h8scm: Add a type cast for printk to correct a warning messageBruce Griffith
Copy a type cast from the other cases of the same switch statement to eliminate compiler warning messages. Change-Id: I8d0a88892f6a5f8e43227ab5f830041894b07f6a Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3543 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28Dinar, H8SCM, H8QGI: Add prototype of get_bus_conf()Bruce Griffith
On Dinar, H8SCM, and H8QGI, add <cpu/amd/amdfam15.h> as an include to pick up the prototype definition of get_bus_conf(). Change-Id: Ie4887670ac52aa194745881362df19cd1d75773e Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3542 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-24AMD: Drop empty root_complexKyösti Mälkki
There are no files to build left under AMD nortbridge/x/root_complex directories. For some cases, even the Kconfig file was no longer sourced. Remove all such references and empty files. For devicetree.cb treat component paths with "/root_complex" in them valid even when the directory does not exists. This is because AMD boards us this dummy chip component as the root node in their devicetree.cb. The generated devicetree file static.c remains unchanged. Change-Id: I9278ebb50a83cebbf149b06afb5669899a8e4d0b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3434 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-17AMD southbridges: Move HAVE_HARD_RESETKyösti Mälkki
All 3 boards with AGESA_HUDSON had HAVE_HARD_RESET with the reset.c file already placed under southbridge/. All 15 boards with CIMX_SBx00 had HAVE_HARD_RESET with functionally identical reset.c file under mainboard/. Move those files under respective southbridge/. Change-Id: Icfda51527ee62e578067a7fc9dcf60bc9860b269 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3486 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-17AMD boards: Clean use of Kconfig optionsKyösti Mälkki
The chip component is unconditionally selected for the mainboard so these uses are superfluous. Change-Id: I84b053ab47f7b1f68e88d968cf305e24bc95f4da Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3485 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-05-09AMD: Reduce stack size from 64 KB to the default of 4 KBPaul Menzel
Apply the following commit to all AMD boards. commit 935850e08293cec1cb27d12358b27285e780566a Author: Stefan Reinauer <reinauer@chromium.org> Date: Mon May 6 16:16:03 2013 -0700 asrock/e350m1: reduce default stack size The stack used on the ASRock E350M1 is significantly less than what we currently set (64k per core). In fact, we use about half of the default stack size (4k) on core 0 and even less on non BSP cores [1]: $ grep stack coreboot_without_patch_but_monotonic_timer.log CPU1: stack_base 002a0000, stack_end 002afff8 CPU1: stack: 002a0000 - 002b0000, lowest used address 002afda8, stack used: 600 bytes CPU0: stack: 002b0000 - 002c0000, lowest used address 002bf75c, stack used: 2212 bytes […] Reviewed-on: http://review.coreboot.org/3209 Please note that AGESA seems to define bigger stack sizes. But these seem to be too much too. $ git grep STACK_SIZE src/vendorcode/amd […] src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:#define BSP_STACK_SIZE 16384 src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:#define CORE0_STACK_SIZE 16384 src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:#define CORE1_STACK_SIZE 4096 src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c: BSP_STACK_SIZE, src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c: CORE0_STACK_SIZE, src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c: CORE1_STACK_SIZE, […] The following command was used to create the patch. $ git grep -l STACK_SIZE src/mainboard/ | xargs sed -i '/STACK_SIZE/,+3d' Change-Id: I36b95b7a6f190b64d0639fc036ce2fb0253f3fa1 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3217 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-08Drop CONFIG_AP_CODE_IN_CARStefan Reinauer
This option has not been enabled on any board and was considered obsolete last time it was touched. If we need the functionality, let's fix this in a generic way instead of a K8 specific way. This was mostly a speedup hack back in the day. Change-Id: Ib1ca248c56a7f6e9d0c986c35d131d5f444de0d8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3211 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-05-08copy_and_run: drop boot_complete parameterStefan Reinauer
Since this parameter is not used anymore, drop it from all calls to copy_and_run() Change-Id: Ifba25aff4b448c1511e26313fe35007335aa7f7a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3213 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-15Drop add_mainboard_resources and HAVE_MAINBOARD_RESOURCES againKyösti Mälkki
These are not defined since commit »Drop HAVE_MAINBOARD_RESOURCES« (1c5071d1) [1] but were unfortunately introduced again in new ports. [1] http://review.coreboot.org/1414 Change-Id: I5eb61628141aefd08779615702d51ca155fa632a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/2707 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-22x86: Unify arch/io.h and arch/romcc_io.hStefan Reinauer
Here's the great news: From now on you don't have to worry about hitting the right io.h include anymore. Just forget about romcc_io.h and use io.h instead. This cleanup has a number of advantages, like you don't have to guard device/ includes for SMM and pre RAM anymore. This allows to get rid of a number of ifdefs and will generally make the code more readable and understandable. Potentially in the future some of the code in the io.h __PRE_RAM__ path should move to device.h or other device/ includes instead, but that's another incremental change. Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-20Supermicro H8SCM: Use SPD read code from F15 wrapperKimarie Hoot
Changes: - Get rid of the h8scm mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2777/ AMD Fam15: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: I575221039ad65a59ae0f93397ef1038b669e81c7 Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/2829 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-20Supermicro H8QGI: Use SPD read code from F15 wrapperKimarie Hoot
Changes: - Get rid of the h8qgi mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2777/ AMD Fam15: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. - select_socket() and restore_socket() started by duplicating sp5100_set_gpio() and sp5100_restore_gpio(), which were in dimmSpd.c. In addition to renaming the functions to more specifically state their purpose, some cleanup and magic number reduction was done. Change-Id: I346ebd8399d4ba3e280576e667fdc62fa75a63b8 Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/2828 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-08Supermicro H8QGI: set up right frequency limits for memory controllerKonstantin Aladyshev
According to BKDG: "Memory controller (MCT) and DRAM controllers (DCTs) additions: • Support for 933 MHz (1866 MT/s) MEMCLK frequency." Change-Id: I6f307ce3fcb355d5445f1ea86def73a41b928a57 Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2589 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-25Supermicro H8SCM & H8QGI: Fix printk warningsMartin Roth
Changes: - Fix printk warnings for these two platforms by getting rid of the l length specifier and casting to unsigned int. This gets rid of a bunch of warnings like this one: agesawrapper.c:279, GNU Compiler 4 (gcc), Priority: Normal format '%lu' expects argument of type 'long unsigned int', but argument 3 has type 'UINT32' [-Wformat] Notes: - This is the same change that was done for Tyan s8226 in change: ddff32eb - http://review.coreboot.org/#/c/2451/ Tyan S8226: Fix printk warnings - I have not tested this change on either of these platforms, I have just compiled it. Change-Id: I46b4c13fde7473cd2a084c7c7cb5c893f1731b02 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2502 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25AMD boards: ACPI DSDT: Use COREBOOT for the OEM Table ID fieldPaul Menzel
The DSDT header contains the fields OEMID and OEM Table ID. See for example ACPI specification 4.0a [1] 5.2.11.1 Differentiated System Description Table (DSDT) on page 135. There Table 5-16 contains the descriptions. Field Byte Length Byte Offset Description =================================================== OEMID 6 10 OEM ID OEM Table ID 8 16 The manufacture model ID. Currently in coreboot there is no common method what to put in these fields. Mostly Intel based boards populate it with "CORE " ore "COREv4" and AMD based boards populate it with the board vendor and model number, abbreviated appropriately to fit into these fields. On most boards the proprietary vendor BIOS seems to leave these fields – displayed with `sudo dmidecode` under System Information – blank To Be Filled By O.E.M. and fill out the Base Board Information with the board vendor and model name. In [2] Jens Rottmann argues that the this is really just the table ID used for naming it and that »99% of the DSDT code is not board specific«. Both approaches seem to have their advantages, but using the second one, developers often seem to forget to update them (for example AMD Thather). The current situation is at least not optimal. and therefore at least unify the string in the OEM Table ID. If unifying the OEM ID is also a good idea this should be done too. If later on it should be decided that the board vendor and model should be used again, this should be somehow derived from Kconfig. The following command was used for the change [3]. $ git grep -l '\/\* TABLE ID \*\/' | xargs sed -i '/TABLE ID/s/"\([^"]*\)"/"COREBOOT"/' This patch is split out from [2]. [1] http://www.acpi.info/spec40a.htm [2] http://review.coreboot.org/#/c/2464/ [3] http://stackoverflow.com/questions/5207838/sed-regex-matching-text-between-to-double-quotes-when-a-certain-text-appears-i Change-Id: Iec98c615ce37f928abc1b500eff5aa865d772cb2 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2472 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-25mainboard.c: Name enable_dev function uniformly `mainboard_enable`Paul Menzel
To reduce the differences between these file name the enabling device function in the directory `src/mainboard` uniformly `mainboard_enable` [1]. Thanks to the awesome help of gnomon and BlastHardcheese in the IRC channel #sed on <irc.freenode.net>. gnomon came up with the following command to do the actual work. $ cd src/mainboard $ for f in */*/mainboard.c ; \ > do src="$(awk '/\.enable_dev = /{v=$NF; sub(/,$/,"",v); print v}' "$f")" ; \ > [[ -z $src ]] && continue ; \ > printf '%s\n' "g/${src}/s/${src}\([,(]\)/mainboard_enable\1/p" w | ed -s "$f" ; \ > done `src/mainboard/digitallogic/msm586seg/mainboard.c` and `src/mainboard/technologic/ts5300/mainboard.c` had to be adapted manually as no comma was used separating the struct members. And with the following statement, gnomon is even more likable! My pleasure entirely. Good luck with coreboot; I'm a big fan of the project. [1] http://www.coreboot.org/pipermail/coreboot/2013-February/074548.html Change-Id: Ife9cd0c2d9cc1ed14afc6d40063450553f06a6c6 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2493 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-22*/acpi_tables.c: Use ALIGN macroPatrick Georgi
At the request of Paul Menzel, I reran an old classic of a coccinelle script: @@ expression E; @@ -(E + 7) & -8 +ALIGN(E, 8) @@ expression E; @@ -(E + 15) & -16 +ALIGN(E, 16) Change-Id: I01da31b241585e361380f75aacf3deddb13d11c3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2487 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-21AMD boards: Fix typo `@brief` in commentPaul Menzel
The following command was used to correct the typo. $ git grep -l @breif | xargs sed -i 's/@breif/@brief/' Change-Id: If0b579279de3c41571b9cda643836f5748a752a2 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2473 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-14sconfig: rename lapic_cluster -> cpu_clusterStefan Reinauer
The name lapic_cluster is a bit misleading, since the construct is not local APIC specific by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-x86 systems without adding new keywords. Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2377 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14sconfig: rename pci_domain -> domainStefan Reinauer
The name pci_domain was a bit misleading, since the construct is only PCI specific in a particular (northbridge/cpu) implementation, but not by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-PCI systems without adding new keywords. Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2376 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-11Supermicro H8QGI: Substract 1 from MMCONF range limitKonstantin Aladyshev
MMCONF space is defined by two config parameters: MMCONF_BASE_ADDRESS (0xF800 0000) MMCONF_BUS_NUMBER (64) Coreboot allocates 1MB per bus, so MMCONF limit should be: 0xF800 0000 + 64*(0x0010 0000) - 1 = 0xFBFF FFFF Current code does not have (-1) component, this makes MMCONF limit equal 0xFC00 FFFF. Not 0xFC00 0000, because according to BKDG lower two bytes of MMIO limit always equal 0xFFFF: MMIOLimit = {MMIOLimitRegister[47:16], FFFFh}. Add (-1) to correct this issue. No functionality change has been experienced. The five times slower RAM speed compared to the proprietary vendor BIOS still remains. Change-Id: I2c6494c28bb8d36e54ceb2aa7d8d965b0103cbe9 Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2193 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-09romcc: Use default romcc flags for most boardsPatrick Georgi
Except for one board, the flags can be derived from CONFIG_MMX and CONFIG_SSE. Change-Id: I64a11135ee7ce8676f3422b2377069a3fa78e24d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2336 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-04AGESA boards: Fix grammar in description of `OemCustomizeInitEarly`Paul Menzel
The following command was used to correct the grammatical mistake. $ git grep -l 'This is the stub function will call' | xargs sed -i s,This is the stub function will call,This stub function will call, '{}' sed: -e Ausdruck #1, Zeichen 6: Nicht beendeter `s'-Befehl As this file seems to have been copied around a lot, it originally seems to have come with the following commit for AMD Persimmon and AMD Inagua. commit 69da1b676cd3f126b27a6fd3c23c557ac1a03961 Author: Frank Vibrans <frank.vibrans@amd.com> Date: Mon Feb 14 19:04:45 2011 +0000 Add IBASE DB-FT1 and AMD Inagua motherboards. Patch 8 of 8. Change-Id: I2e6630a5172738b01e6def7062284f167e5508b1 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2268 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-16Fix high dword of MTRR mask set with CONFIG_CPU_ADDR_BITSMartin Roth
Bits were being shifted off the end of the mask accidentally. This results in all masks being 32 bits wide instead of 48. Change-Id: I5f4d1b6a323df1aa4568ff4491f82447b8a2f839 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2146 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Marc Jones <marcj303@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-01-11AMD: Set the mask of MTRR according to CONFIG_CPU_ADDR_BITSZheng Bao
The high bits of mtrr mask are MBZ (Must be zero). Writing 1 to these bits will cause exception. So be carefull when spread this change. The supermicro/h8scm needs more work. Currently it is set as it was. We need to check if the F10 and F15 have different value. Change-Id: I2dd8bf07ecee2fe4d1721cec6b21623556e68947 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1661 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-02Supermicro H8QGI: Pass callout pointer to AmdReadEventLog functionAladyshev Konstantin
I have issues when AmdReadEventLog function tries to use BiosCallouts interface. So it is necessary to provide callout pointer to this function. Change-Id: I4080e5f07d5d28c41688b2a7deff944b7a0f7bf7 Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2064 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com> Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2012-12-28Supermicro H8QGI: Add onboard VGA to devicetree.cbAladyshev Konstantin
Supermicro H8QGI has integrated Matrox G200 16MB DDR2 graphics. List it in devicetree.cb to mark it as onboard VGA to coreboot. This change makes menuconfig option "Use onboard VGA as primary video device" work. Change-Id: Ia6b9f60e3ae705689f22babd544ad6e628a85df1 Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2042 Tested-by: build bot (Jenkins) Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-28Supermicro H8QGI: fix bus_sp5100[] clear in get_bus_conf.cAladyshev Konstantin
Fix little mistake in get_bus_conf code Change-Id: I8c09e501082caa0a20266b007c0744630a356de0 Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2046 Tested-by: build bot (Jenkins) Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-28BiosCallOuts: Replace REQUIRED_CALLOUTS define with flexible variableAladyshev Konstantin
Size of BiosCallouts[] struct can be calculated as: CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); There is no longer need for REQUIRED_CALLOUTS define. Originally that change was done for AMD Persimmon in commit d7a696d0f229abccc95ff411f28d91b9b796ab74 Author: efdesign98 <efdesign98@gmail.com> Date: Thu Sep 15 15:24:26 2011 -0600 Persimmon updates for AMD F14 rev C0 without deleting the define. This was ported to some of the other boards and for some the define was not removed. The AMD Inagua, Parmer and Thatcher boards were already adapted but the define was left in. So just remove it for those. Tested on Supermicro H8QGI. Change-Id: Ia09795579a1170fa20ab94a30feb1af6821153d2 Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2049 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-21Supermicro H8QGI: Fix routing from 16 to 55 in ACPI tableAladyshev Konstantin
H8QGI board has 2 IO-APICS with 56 IRQ’s: IOAPIC[0]: GSI 0-23 - SB700 southbridge IOAPIC[1]: GSI 24-55 - RD890 northbridge `gDefaultApicDeviceInfoTable[]` structure in northbridge code vendorcode/amd/cimx/rd890/nbIoApic.c has IO-APIC interrupt mapping for HT and IOMMU set to last 31 IRQ pin (24+31=55). CONST APIC_DEVICE_INFO gDefaultApicDeviceInfoTable[] = { // Group Swizzling Port Int Pin {0, 0, 31}, //HT {0, 0, 31}, //IOMMU […] Also the same value (55) can be found in original Supermicro BIOS ACPI DSDT. Change-Id: Ie26da1f773716d1b7f5f5f884050ae799afc0b7e Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2047 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-01Drop TINY_BOOTBLOCKKyösti Mälkki
Change-Id: I38ea2ed2be4d9240ec8cb6d5dc5b3cc578cdaefb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1963 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-30Supermicro h8scm: add agesa version of supermicroSiyuan Wang
Supermicro h8scm has a C32 CPU socket, the details of this board is: http://www.supermicro.com/Aplus/motherboard/Opteron4100/SR56x0/H8SCM-F.cfm We are planning to replace legacy C32 code with agesa and the h8scm_fam10 do not support family 15 CPU, so we update this mainboard with this patch. This code supports memory at 800M Hz of f10 CPU, bu f15 CPU does not has this limitation. If you want to change the frequency of memory, please edit the macros "BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT" and "BLDCFG_MEMORY_CLOCK_SELECT" in src/mainboard/supermicro/h8scm/buildOpts.c Change-Id: I9ca9e70d7f3e82c07e7d36695bf31008db152afb Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1510 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-29Drop empty mainboard.cKyösti Mälkki
Change-Id: Idcf9349d96297b8cb0ea1e68769e02659ac16ab8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1933 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-29Drop empty mainboard_opsKyösti Mälkki
Change-Id: I24866142eebcb8fdbc7e21f5b2f364a8d1b264b3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1932 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-28amdk8/amdfam10: Use CAR_GLOBAL for sysinfoPatrick Georgi
This gets rid of the somewhat unstructured placement of AMD's sysinfo structure in CAR. We used to carve out some CAR space using a Kconfig variable, and then put sysinfo there manually (by "virtue" of pointer magic). Now it's a variable with the CAR_GLOBAL qualifier, and build system magic. For this, the following steps were done (but must happen together since the intermediates won't build): - Add new CAR_GLOBAL sysinfo_car - point all sysinfo pointers to sysinfo_car instead of GLOBAL_VAR - remove DCACHE_RAM_GLOBAL_VAR_SIZE - from CAR setup (no need to reserve the space) - commented out code (that was commented out for years) - only copy sizeof(sysinfo) into RAM after ram init, where before it copied the whole GLOBAL_VAR area. - from Kconfig Change-Id: I3cbcccd883ca6751326c8e32afde2eb0c91229ed Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1887 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-27Remove AMD special case for LAPIC based udelay()Patrick Georgi
- Optionally override FSB clock detection in generic LAPIC code with constant value. - Override on AMD Model fxx, 10xxx, agesa CPUs with 200MHz - compile LAPIC code for romstage, too - Remove #include ".../apic_timer.c" in AMD based mainboards - Remove custom udelay implementation from intel northbridges' romstages Future work: - remove the compile time special case (requires some cpuid based switching) - drop northbridge udelay implementations (i945, i5000) if not required anymore (eg. can SMM use the LAPIC timer?) Change-Id: I25bacaa2163f5e96ab7f3eaf1994ab6899eff054 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1618 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27Drop duplicate files that prevent building without ramstage.aStefan Reinauer
When dropping ramstage.a duplicate symbols in ramstage will start breaking the build. Hence drop all the duplicate functions implemented by mainboards that have those functions in generic or component code already. Change-Id: I5cf8245c67b6f0f348388db54256d28f47017a61 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1865 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-11-16Fix PIRQ routing abstractionStefan Reinauer
intel_irq_routing_table is a local structure that should not be used globally, because it might not be there on all mainboards. Instead, the API has to be corrected to allow passing a PIRQ table in where needed. Change-Id: Icf08928b67727a366639b648bf6aac8e1a87e765 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1862 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-16Fix Kconfig GENERATE_*_TABLE usageStefan Reinauer
Some boards selected GENERATE_ instead of HAVE_ Change-Id: I450c22d7b044f0c88c21692246d452d516a68a83 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1841 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-16Drop Kconfig variable BOARD_HAS_HARD_RESETStefan Reinauer
hard_reset was indeed consolidated and moved into the southbridge code a while ago, but the config variable was still kept alife, with some duplicate code. Change-Id: I60d4a87de916667f6e89353dfbe1a7b9eca380f7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1837 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-16Drop unneeded BOARD_HAS_FADT optionStefan Reinauer
Change-Id: Iaaeee87d70cf052bc7980007cdf1f7dda88b3623 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-16Drop CONFIG_HAVE_BUS_CONFIG, clean up KconfigStefan Reinauer
This patch is the beginning of a Kconfig cleanup series - drop CONFIG_HAVE_BUS_CONFIG and add get_bus_conf.c if it exists in the mainboard directory - drop duplicate ACPI_SSDTX_NUM from mainboard Kconfig if it only defines the defaul value of 0 - Add mptable.c, fadt.c, reset.c and ssdtX.asl when they exist, not based on some Kconfig magic Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ia14a7116dad6a724af7e531920fee9a51fd0b200 Reviewed-on: http://review.coreboot.org/1832 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-09Get rid of hard coded strings in ACPI tablesStefan Reinauer
(cosmetical) Change-Id: I3e01d8fbf2d71abcfcbe47efedd2184566c91df7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1748 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-06Drop redundant CHIP_NAME in mainboard.cKyösti Mälkki
Compose the name from Kconfig strings instead. As the field is for debug print use only, a minor change in the output should do no harm. The strings no longer include word "Mainboard". Change-Id: Ifd24f408271eb5a5d1a08a317512ef00cb537ee2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1635 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-09-19C32 legacy code: change CONFIG_CPU_AMD_SOCKET_C32 to ↵Siyuan Wang
CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA Currently the C32 has some legacy boards which use the old C32 code. We need to seperate them. CONFIG_CPU_AMD_SOCKET_C32 was used in legacy code before. But it is not a good idea, so we change the code as follows: So we use CONFIG_CPU_AMD_SOCKET_C32 to identify mainboard which uses agesa code, and use CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA to identify mainboard which uses legacy code. Change-Id: If6114bf8912e78b7732f25a1adfb2e4d8eb10ee4 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1497 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-08-25Fix mptable build troublesKyösti Mälkki
A missing mptable.c file got passed jenkins, got merged and broke the build. Hopefully finally fix this. Deletes unused files: src/mainboard/asus/dsbf/mptable.c src/mainboard/supermicro/x7db8/mptable.c Change-Id: Ie81f5a6c4c69ab381f86a243bc8874395e69ee26 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1486 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-08Cleanup coreboot memory table includesKyösti Mälkki
The includes removed here were previously required for struct lb_memory and lb_add_memory_range(). Change-Id: Ie6c0d4ef55c2225aa709cf3fbad30ff1080e3610 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1391 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2012-08-08Drop HAVE_MAINBOARD_RESOURCESKyösti Mälkki
These existed to provide a hook to add reserved memory regions in the coreboot memory table. Reserved memory are now added as resources. Change-Id: I9f83df33845cfa6973b018a51cf9444dbf0f8667 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1414 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-07-31Revert "remove CONFIG_SERIAL_CPU_INIT"Sven Schnelle
This reverts commit 78efc4c36c68b51b3e73acdb721a12ec23ed0369. The broadcast patch was reverted, so this commit should also be reverted. The reason for reverting the broadcast patch: It turned out that sending IPIs via broadcast doesn't work on Sandybridge. We tried to come up with a solution, but didn't found any so far. So revert the code for now until we have a working solution. Change-Id: I05c27dec55fa681f455215be56dcbc5f22808193 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1380 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-26Drop mainboard chip.hStefan Reinauer
mainboard_config never worked right, at least not since we've had sconfig. Hence, drop mainboard/<vendor>/<device>/chip.h and fix up the mainboards that tried to use it anyways. Change-Id: I7cd403ea188d8a9fd4c1ad15479fa88e02ab8e83 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1359 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-14Supermicro X7DB8: Use autogeneration of mptableSven Schnelle
And fix the wrong indenting of devicetree.cb while at it. Change-Id: Idbb19fb5d7155f44675098e79920caf65191c239 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1222 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-04Supermicro X7DB8: add w83793 Hardware monitorSven Schnelle
used for fan control and thermal management on that board. Change-Id: I4e5c986ab6174b7a356d682e21732c46181af211 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1167 Tested-by: build bot (Jenkins)
2012-07-02remove CONFIG_SERIAL_CPU_INITSven Schnelle
The new broadcast code doesn't support serial init - if a CPU needs serial init, this should be handled in the model specific CPU init code. Change-Id: I7cafb0af10d712366819ad0849f9b93558e9d46a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1140 Tested-by: build bot (Jenkins)
2012-06-23Add Supermicro X7DB8 motherboardSven Schnelle
This adds basic supported for the Supermicro X7DB8. Basic means that almost all onboard peripherals are working. Known problems are: - mptable needs to be written dynamically. If you plan to use Add on cards, modify mptable.c according to your needs. A patch to add generic mptable autogeneration based on devicetree is coming up. Change-Id: I5eaac32a8bafa69a05929cf08d869127b9464661 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/493 Tested-by: build bot (Jenkins)
2012-05-10Unmark source files as executablesAlec Ari
Change source file modes from 755 to 644 The following files have been grepped for changes: *.c *.h *Kconfig* *Makefile* Change-Id: I275f42ac7c4df894380d0492bca65c16a057376c Signed-off-by: Alec Ari <neotheuser@ymail.com> Reviewed-on: http://review.coreboot.org/1023 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-08Clean up #ifsPatrick Georgi
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} + Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} + Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} + Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} + (and some manual changes to fix false positives) Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1004 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <martin@se-eng.com>
2012-04-27Move top level pc80 directory to drivers/Stefan Reinauer
There is no reason for this to be a top level directory. Some stuff from lib/ should also be moved to drivers/ Change-Id: I3c2d2e127f7215eadead029cfc7442c22b26814a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/939 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-20Refactor some alignment handlingPatrick Georgi
Made using coccinelle: @@ expression E; @@ -(E + 7) & -8 +ALIGN(E, 8) @@ expression E; @@ -(E + 15) & -16 +ALIGN(E, 16) Change-Id: I071d2c98cd95580d7de21d256c31b6368a3dc70b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/910 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-19Fix the blank in acpi_tables.czbao
Hope no more blank issue is got from future copy-paste. Change-Id: I5eb50e8232e339e7039a15054606aaff6b7ebc52 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/907 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-04-19Fix messy code in ALIB creationzbao
Fix the copy-paste typo in ALIB table creation. ssdt is useless here. Change-Id: I250066eb5f755275f75c37789ce8760de35b046b Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/885 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-04-19Leverage the Pstate table created by AGESA.zbao
The name of processor created by AGESA is P00n, whose P is BLDCFG_PROCESSOR_SCOPE_NAME(is 'C' if it is undefined.) and n starts from 0. The dsdt should be aligned with that. This feature has only been tested on persimmon. The changes on all the other boards were propagated. Change-Id: I8c3fa4b94406d530d2bed8e9a1f42b433bbec3ec Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/884 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-04-16ACPI HEST table.zbao
HEST feature starts from ACPI 4.0. HEST is one of four kinds of tables of ACPI Platform Error Interfaces (APEI). In Windows world, APEI is called Windows Hardware Error Architecture (WHEA). APEI consists of four separate tables: 1. Error Record Serialization Table (ERST) 2. BOOT Error Record Table (BERT) 3. Hardware Error Source Table (HEST) 4. Error Injection Table (EINJ) All these 4 tables have the same header as FADT, MADT, etc. They are pointed by RSDP. For the HEST, it contains the error source. The types of them are defined as type description 1. Machine Check Exception (MCE) 2. Corrected Machine Check (CMC) 3. NMI Error 6. PCI Express Root Port AER 7. PCI Express Device AER 8. PCI Express Bridge AER 9. Generic Hardware Error Source Error source types 3, 4, and 5 are reserved for legacy reasons and must not be used. Currently AMD board only provide part of "Machine Check Exception (MCE)" & Corrected Machine Check (CMC)". we need to provide the header of each error source. Other types of Error Sources is in TODO list. Only persimmon is tested. Linux can add HEST feature. The dmesg says, ACPI: HEST 0000000066fe5010 00198 (v03 CORE COREBOOT 00000000 CORE 00000000) ...... HEST: Table parsing has been initialized. No more message is got. Windows can boot with this patch. Havent found a way to test it. Change-Id: I447e7f57b8e8f0433a145a43d0710910afabf00f Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/888 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-03-31Drop obsolete TINY_BOOTBLOCKKyösti Mälkki
Change-Id: I0cbb5f7fce91fe65fe8daad00fc43e68337783b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/832 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-08Unify Local APIC address definitionsPatrick Georgi
We used several names for that same value, and hardcoded the value at some more places. They're all LOCAL_APIC_ADDR now (except for lapic specific code that still uses LAPIC_DEFAULT_BASE). Change-Id: I1d4be73b1984f22b7e84681edfadf0588a7589b6 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/676 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-29AMD southbridge: remove sp5100Kyösti Mälkki
Southbridge SP5100 support was compiled with SB700 code, but static device info structure would use sp5100/chip.h. To solve this drop support for separate chip sp5100 and adjust the relevant Kconfig options. Removes chip directory: src/southbridge/amd/sp5100/ Rename Kconfig option from: SOUTHBRIDGE_AMD_SP5100 to: SOUTHBRIDGE_AMD_SUBTYPE_SP5100 Change-Id: I873c6ad3624ee69165da6ab7287dfb7e006ee8e8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/679 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-22ACPI: More ../../.. removalPatrick Georgi
CPP is ran with src/ as part of its search path, so using <northbridge/...> and the like is safe. Change-Id: I644d60190ac92ef284d5f0b4acf44f7db3c788ee Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/649 Tested-by: build bot (Jenkins)
2012-02-22Remove old AMD fam10 fixme commentMarc Jones
The family10 code had a very slow decompress before the cache settings were fixed. This has been fixed for some time. Remove all the old messages from the serial stream. Change-Id: I476efe1a430f702af394734f354ff69bd053f1d2 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/672 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-02-17nvidia/mcp55: Move HAVE_HARD_RESET to southbridgePatrick Georgi
No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: Ibfb7b294aa5007ac2f767d85e090572f85148bad Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/659 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-02-17intel/i82801ex: Move HAVE_HARD_RESET to southbridgePatrick Georgi
No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: I83105e92d1cc5d2d12aede564a1ab9c5d912ac56 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/664 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-02-16HWM: Nuvoton W83795G/ADG HWM supportKerry Sheh
Supermicro H8QGI-F 1 Unit Chassis contain 9 system Fans, they are controled by a separate W83795G Hardware Monitor chip. This patch adds Nuvoton W83795G/ADG HWM support. Change-Id: I8756f5ed02dc2fa0884cde36e51451fd8aacee27 Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/569 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-16Mainboard: Supermicro/h8qgi mainboard updateKerry Sheh
1. Supermicro H8QGI mainboard update to support both family10 Revison D processor and family15 model 00-0fh processor in one binary image. 2. RD890/SR56X0 IO hub CIMX wrapper support. 3. SP5100/SB700 southbridge CIMX wrapper support. Both 8 cores and 16 Cores InterLagos Opteron Processor are tested on this platform. Debian Linux 5.0 and Windows Server 2008 R2 Statdard are tested. Change-Id: Iaad8c9b08310813441188deee6797b3f6dd37d6d Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/567 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-09Remove no-op Makefiles under mainboard directoryKyösti Mälkki
Patch removes following files: src/mainboard/amd/serengeti_cheetah/Makefile.inc src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc src/mainboard/broadcom/blast/Makefile.inc src/mainboard/hp/dl145_g1/Makefile.inc src/mainboard/msi/ms9282/Makefile.inc src/mainboard/supermicro/h8dme/Makefile.inc src/mainboard/tyan/s2881/Makefile.inc src/mainboard/tyan/s2892/Makefile.inc src/mainboard/via/epia-m700/Makefile.inc Change-Id: I020776313abff1772be38afc896af51ca5ab6453 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/612 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-07Delete hard-coded driver includesKyösti Mälkki
Driver components are conditionally included in the build using the Kconfig options. Change-Id: I05417ee263a5b82e947600482dfb68f7a3f52d58 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/610 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-12-02Change AMD vendorcode buildKyösti Mälkki
Apply the normal method of recursively including subdirectories for src/vendorcode. Remove redundant references under mainboard and northbridge. Change-Id: I914a6e262ed2abe83f407df36fe5c1af5eb4bcb0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/468 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-06Fix typoPatrick Georgi
Change-Id: I195ea15ddbc725091e32191fac3b84d01b456580 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/410 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-01remove trailing whitespaceStefan Reinauer
Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/364 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-01Remove XIP_ROM_BASEPatrick Georgi
The base is now calculated automatically, and all mentions of that config option were typical anyway (4GB - XIP_ROM_SIZE). Change-Id: Icdf908dc043719f3810f7b5b85ad9938f362ea40 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/366 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-30remove usbdebug.h include from mainboard/romstage codeSven Schnelle
No romstage is supposed to use usbdebug functions/defines directly, so remove all those includes. The usb code is now called and setup from console code. Change-Id: I9b1120d96f5993303d6b302accc86e14a91f7a9f Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/354 Tested-by: build bot (Jenkins)
2011-10-28Get rid of the old romstage-as-bootblock ROM layoutPatrick Georgi
This change removes CONFIG_TINY_BOOTBLOCK, CONFIG_BIG_BOOTBLOCK, and all their uses, assuming TINY_BOOTBLOCK=y, BIG_BOOTBLOCK=n. This might break a couple of boards on runtime, but so far, fixes were quite simple. There's a flag day: Code that relies on CONFIG_TINY_BOOTBLOCK must be adapted. Change-Id: I1e17a4a1b9c9adb8b43ca4db8aed5a6d44d645f5 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/320 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-13mptable: Refactor mptable generation some morePatrick Georgi
The last couple of lines of every mptable function were mostly identical. Refactor into common code, a new function mptable_finalize. Coccinelle script: @@ identifier mc; @@ ( -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); -printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); -return smp_next_mpe_entry(mc); +return mptable_finalize(mc); | -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); -return smp_next_mpe_entry(mc); +return mptable_finalize(mc); ) Change-Id: Ib2270d800bdd486c5eb49b328544d36bd2298c9e Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/246 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13mptable: Get rid of fixup_virtual_wirePatrick Georgi
As stated in some code files, fixup_virtual_wire was established to avoid touching 200 invocations of the mptable code. Let Coccinelle do it: @@ type T; identifier v; @@ -void fixup_virtual_wire(T v) -{ ... } @@ expression A; identifier v; @@ -v = smp_write_floating_table(A); +v = smp_write_floating_table(A, 0); @@ expression A; identifier v; @@ -v = smp_write_floating_table(A, 0); -fixup_virtual_wire(v); +v = smp_write_floating_table(A, 1); Change-Id: Icad8a063380bf4726be7cebb414d13b574112b14 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/245 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13mptable: Refactor lintsrc generationPatrick Georgi
We copied pretty much the same code for generating mptable entries for local interrupts (with some notable exceptions). This change moves these lines into a generic function "mptable_lintsrc" and makes use of it in many places. The remaining uses of smp_write_lintsrc should be reviewed and replaced by mptable_lintsrc calls where possible, and smp_write_lintsrc made static. This patch was generated using Coccinelle: @@ expression mc; expression isa_bus; @@ -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); +mptable_lintsrc(mc, isa_bus); @@ expression mc; expression isa_bus; @@ -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x0); -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x1); +mptable_lintsrc(mc, isa_bus); @m@ identifier mc; expression BUS; @@ -#define IO_LOCAL_INT(type, intr, apicid, pin) smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, BUS, (intr), (apicid), (pin)); ... -IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); -IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); +mptable_lintsrc(mc, BUS); Change-Id: I97421f820cd039f5fd753cb0da5c1cca68819bb4 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/244 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-09Do not compile nuvoton superio for all boardAlexandru Gagniuc
The nuvoton WPCM450 code is compiled for all boards regardless of whether or not they use it. Compile it only for boards needing it. Change-Id: Iaf4cf2c479eb3238863f0771be799f02a8cc3421 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/129 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She <shekairui@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-22Add the SuperMicro H8QGI platformefdesign98
This set adds support for the SuperMicro H8QGI mainboard. It is a publicly available 4 socket board using AMD Family 10 cpus and AMD SR5650 and SB700 bridges. Change-Id: I196704f79db4c45382559c5ee0619dc8d96ff140 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/108 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She <shekairui@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-22Update AMD SR5650 and SB700efdesign98
This updates the code for the AMD SR5650 and SB700 southbridges. Among other things, it changes the romstage.c files by replacing a .C file include with a pair of .H file includes. The .C file is now added to the romstage in the SB700 or SR5650 Makefile.inc. file to the romstage and ramstage elements. This particular change affects all mainboards that use the SB700, and their changes are include herein. These mainboards are: Advansus a785e, AMD Mahogany, Mahogany-fam10, Tilapia-fam10, Asrock 939a785gmh, Asus m4a78-em, m4a785-m, Gigabyte ma785gm, Iei Kino-780am2-fam10 Jetway pa78vm5 Supermicro h8scm_fam10 The nuvoton/wpcm450 earlysetup interface is changed because the file is no longer included in the mainboard romstage.c files. Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/107 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She <shekairui@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-04-20run uart_init() from console_init, just like the other console ↵Stefan Reinauer
initialization functions. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-18* Set USBDEBUG_DEFAULT_PORT in all southbridges and use that valueStefan Reinauer
to unify calls to *_enable_usbdebug() * rename *_enable_usbdebug() to enable_usbdebug() * move enable_usbdebug() to generic romstage console init code and drop it from the individual romstage.c files. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-10In 2007 Adrian Reber suggested that we drop ASSEMBLY in favor of __ASSEMBLER__.Stefan Reinauer
http://www.coreboot.org/pipermail/coreboot/2007-September/024665.html It's about time we follow this advice. Also move some manually set __PRE_RAM__ defines (ap_romstage.c) to the Makefile and drop unused CPP define Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-28Add support for Supermicro H8scm.Zheng Bao
It is AMD C32 + SR5650 + SP5100. It is created by svn copy amd/tilapia_fam10. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6466 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-08Enable mahogany_fam10 and Kino family 10h to run the SB HT link at the ↵Scott Duplichan
expected HT3 frequency and width by matching the BUID swap list to the production BIOS. In addition, the BUID swap list has been moved into the project-specific file romstage.c for the other 13 AMD family 10h projects as well. For projects using a desktop AMD family 10h processor, pasting in the mahogany_fam10 swap list will likely allow HT3 operation. This should be confirmed on real hardware before commiting any swap list change. A different swap list will be needed for server projects. For serengeti_cheetah_fam10, a reference BIOS swap list to try is: 0x00, 0x0A, 0x00, 0x06, 0xFF, 0x0A, 0x06, 0xFF. The patch makes these changes: 1) Remove the BUID swap list from ht_wrapper.c and put it in each of 15 romstage.c files where it is used (AMD family 10h projects). 2) Add a prototype to amdfam10.h. 3) Modify the swap list and test in real hardware for mahogany_fam10 and kino family 10h and confirm HT3 operation for the SB link. Abuild tested. Signed-off-by: Scott Duplichan <sc...@notabs.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-01Use subsystem id from devicetree.cb instead of Kconfig and moveSven Schnelle
all boards to the new config scheme. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-26Make AMD Fam10h CPU microcode updates optional in Expert modeXavi Drudis Ferran
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 20:00:14 +0000