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Fix PNP warning about missing devicetree entry for SUART1/2 by setting
register 0xF0 to a sane (default) value.
Change-Id: Ie852696aae09b9b03cebd6c3d8cbbd53a7138d89
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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When specifying _PAD_CFG_STRUCT with raw hex values, a logical reset
value of 0x0 is only defined for GPD pads. For any other GPIOs this maps
to 0x3.
On the Supermicro X11 boards a value of 0x0 is set for GPP_D22 and
GPP_F23, triggering the error "gpio_pad_reset_config_override: Logical
to Chipset mapping not found".
Set the right value (0x3<<30) for the affected GPIOs.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I3ae17dfc4d90f88f5b8bc5bee49740745778a91a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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SUART3/4 are unused on this board (verified by checking registers on
vendor BMC firmware). Further they break the console for an unknown
reason. Thus disable them.
Change-Id: I30bb8184d03ee1037d9ec33eb1d93ee540563fc5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38818
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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SUART3/4 are unused on this board (verified by checking registers on
vendor BMC firmware). Thus drop the remaining settings.
Change-Id: I2ababd92fcd7016c508aa3119e798f75eeb90a1c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38817
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With UART3 and 4 enabled, the serial console in LinuxBoot crashes. This
is a short-term solution until we found and fixed the original bug.
Change-Id: I75cb387ef12944232b51f6d8d41810bb27754b05
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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Even though the vendor firmware enables the i8042 I/O port, it doesn't
feed valid data to those, but instead uses USB HID devices.
Disable the KBC port in SuperI/O and report no KCS port using FADT.
Fixes:
* Fixes error message in Linux that i8042 keyboard couldn't be enabled.
Tested on Supermicro X11SSH-TF:
The virtual remote managment console still works.
Change-Id: I1cdf648aa5bf1d0ec48520fa1e45bdaf043cb45d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This adds another x11 series board, the X11SSM-F, which is similiar to
X11SSH-TF but differs in PCIe interfaces/devices, GPIO settings and
Ethernet interfaces.
Change-Id: I24e6f0f41a844652f88b562285b26beef311a2c9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner
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Move USB ports from the common devicetree to the variants' overridetree
as they differ at least for X11SSH-TF and X11SSM-F.
Change-Id: I9bee3a8f6185296cadcee013a8dbe8dca256bf0b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Make the the FSP Parameter PchHdaVcType a devicetree setting and make
use of it in the devicetrees of all boards that currently set it.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ibafc3b6bd2495658f2bd634218042ec413a89f5e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
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This removes the "ifdef ACPI" which is not needed here as we currently
don't include gpio.h in any asl file.
Change-Id: I803bbee5933eda9423a9bc9fcaea9e905e3ac78e
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35543
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Most of the X11 boards with socket LGA1151 are basically the same boards
with just some minor differences like different NICs (1 GbE, 10 GbE),
number of NICs / PCIe ports etc.
There are about 20 boards that can be added, if there is a community for
testing.
To be able to add more x11 boards easily like x11ssm (see CB:35427) this
restructures the x11ssh tree to represent a "X11 LGA1151 series". There
were multiple suggestions for the structure like grouping by series
(x10, x11, x...), grouping by chipset or by cpu family.
It turned out that there are some "X11 series" boards that are
completely different. Grouping by chipset or cpu family suffers from the
same problem. This is why finally we agreed on grouping by series and
socket ("X11 LGA1151 series").
The structure uses the common baseboard scheme, while there is no "real"
baseboard we know of. By checking images, comparing logs etc. we came to
the conclusion that Supermicro does have some base layout which is only
modified a bit for the different boards.
X11SSH-TF was moved to the variants/ folder with it's gpio.h. As we
expect the other boards to have mostly the same device tree, there is a
common devicetree that gets overridden by each variant's overridetree.
Besides that some very minor modifications happened (formatting, fixing
comments, ...) but not much.
Documentation is reworked in CB:35547
Change-Id: I8dc4240ae042760a845e890b923ad40478bb8e29
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35426
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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