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2020-12-30mb/supermicro/x11ssm-f: configure "POST complete" gpio for IPMI driverMichael Niewöhner
Configure the "POST complete" gpio in the devicetree for the BMC/IPMI driver. Also add the pad to early gpio config, since it has an external pull-up, which is wrong and would confuse the BMC. Set the pad's initial value to zero since the "POST complete" signal is active-high and shall be set by the IPMI/BMC driver. Test: Boot the machine via the BMC web interface and check that sensors get read correctly by the IPMI firmware when the payload starts. Tested successfully. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I6409b2aca90585e44ee5d32df0ae73b259443f32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-30mb/supermicro/x11ssm-f: configure the BMC jumper JPB1Michael Niewöhner
Set `bmc_jumper_gpio` to the JPB1 gpio to enable/disable BMC/IPMI according to its value. Test: Boot with jumper set to each enabled and disabled and check debug log if IPMI gets enabled/disabled accordingly. Tested successfully. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I8581556d915cbad2c743a79db273479ba55798fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/48095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-11mb/supermicro/x11ssm-f: disable unconnected and unused/strap-only padsMichael Niewöhner
There is a whole bunch of pads being configured by the vendor firmware that are either unconnected due to unpopulated resistor pads, only connected to test points for vendor debugging purposes or just used as strap. Configure them as NC with an appropriate pull to disable the RX/TX functions. The pads have been determined by dissecting a dead board. This patch has been tested thoughroughly on a machine, normally used productive, to see if any issues arise. No problems occurred at all. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I06b942e3182469f87e41914c893e5b485ccca420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-10mb/supermicro/x11ssm-f: enable AER for PCIe root portsMichael Niewöhner
Follow vendor and enable Advanced Error Reporting for PCIe root ports. This enabled the Linux AER driver, which handles PCIe error conditions. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I9d9b5afca0ca891e2812445db1d42a46ba16199e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48369 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10mb/supermicro/x11ssm-f: add subsystem ids to PCI ports and devicesMichael Niewöhner
Add the subsystem ids to PCI ports and devices, which were dumped on vendor firmware using `lspci`. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Idb36c5c72e1b0b8303439ae5dce772822f551d2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/48368 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10mb/supermicro/x11ssm-f: enable LTR for all root portsMichael Niewöhner
Follow vendor and enable LTR on all root ports to optimize for devices' latency requirements and also optimize power management while preventing failure due to wrongly guessing idle states, which happens without LTR. Tested successfully. No errors show up in dmesg. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I8f72087c71e291d2412dc7b3e16ee7f419e2ca0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/48367 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10mb/supermicro/x11ssm-f: (re)configure unconnected padsMichael Niewöhner
Correct unconnected pads that are configured different currently by copying vendor configuration while porting the board. Add internal pull resistors to all unconnected pads, that do not have an external pull resistor, to prevent floating. The pads have been determined by dissecting a dead board. This commit only changes pads, that are not connected at all and don't have any via, so we can be absolutely sure there is no other connection. Change-Id: I991fe270b42f430f7447712236e0f80b3d5bba2a Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-10mb/supermicro/x11ssm-f: (re)configure and document various padsMichael Niewöhner
(Re)configure various pads found by dissecting a dead board and vendor firmware, as well as the BMC firmware: - GPP_B14: input connected to jumper JBR1 - could be used to implement "BIOS Recovery" ("Top-Block Swap") functionality; external pull-up - GPP_C20: output to BMC alert CPU_THROTTLED# - can be used to notify the BMC about a thermal throttling event. Not implemented in vendor firmware. - GPP_C23: input connected to the CPU's CATERR# output; external pull-up Not actively used by vendor firmware. - GPP_D1: output connected to on-board and front panel power LEDs - GPP_D18: output connected to PERST# of both CPU PCIe Slots. Can be used for testing/debugging only, since it resets both slots at once. Not actively used by vendor firmware. - GPP_D19: output connected to PERST# of both PCH PCIe Slots. Can be used for testing/debugging only, since it resets both slots at once. Not actively used by vendor firmware. - GPP_D22: input connected to the BMC enable/disable jumper JPB1; Will be used later in CB:48096 and CB:48097; external pull-up - GPP_G0 - GPP_G3: dedicated/integrated CPU switching; probably not useful, since the IGD is not connected to any ports on this board. External pulls ensure correct function of a dGPU even without driving the gpios. Not used by vendor firmware. - GPP_G12 - GPP_G16: inputs for binary SKU_ID; external pulls - GPP_G20: PWRFAIL# input from JPI2C1 (pin 3); external pull-up; Not used by vendor firmware. Also add comments for documentation. While at it, mark ME-owned pads as reserved. Change-Id: I9f9328e9ce6f7e291b171f776bb98bc617b64b93 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-12-04mb/supermicro/x11ssm-f: correct trigger for SMI/NMI interrupt inputsMichael Niewöhner
All four SMI/NMI interrupt inputs have an external pull-up resistor and get triggered by pulling the line low. Thus, correct the trigger to active-low. Also document the signals by adding appropriate comments. The pads' connections have been determined by dissecting a dead board. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Id1a8c1e0b9fe723a15d04a88d565a53eeba9b085 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48093 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04mb/supermicro/x11ssm-f: drop NMI overridesMichael Niewöhner
Drop the NMI overrides, since NMI now gets configured in gpio common code. Also remove the variant init mechanism, which is unused now. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I02e0c679f9aafe33108320a8dfc62dcb278202ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/48092 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-29mb/supermicro/x11-lga1151-series: rework gpio setup to not use headersMichael Niewöhner
Rework gpio setup for the board series to not use headers but stage-specific compilation units. Tested successfully on X11SSM-F. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Ic62ce4335af605c081ef288e892441585ff2bd3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-11-29mb/supermicro/x11-lga1151-series: switch from dev.init to mb_ops.initMichael Niewöhner
GPIO needs to be initialized before the IPMI device gets initialized, so the GPIOs can be read/set by the code in CB:48096 and CB:48094. Thus, use mainboard_ops.init for GPIO configuration instead of using the indirection via a mainboard_enable function. To make it more visible, that we use chip.init, rename `mainboard_init` to `mainboard_chip_init`. Tested successfully on X11SSM-F including the IPMI changes. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I192e69a34fa262b38bc40a95fb11c22a4041d0ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/48083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-28mb/supermicro/x11ssm-f: drop unneeded ITSS overrideMichael Niewöhner
The ITSS override is not needed for LPC_CLKOUT* pads. Drop it. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I3dbbc8944751779151dcd4f92fb870d937801d69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48084 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-28mb/supermicro/x11-lga1151-series: restructure and clean up devicetreeMichael Niewöhner
Drop zero-value devicetree options and move PcieRpEnable options down to the corresponding devices. Test: built with TIMELESS=1; binaries remain identical Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I9285d786e973621a732e2627c734adc930e54207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-21soc/intel,mb/*: get rid of legacy pad macrosMichael Niewöhner
Get rid of legacy pad macros by replacing them with their newer equivalents. TEST: TIMELESS-built board images match Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-29mb/supermicro/x11-lga1151-series: correct superio interruptsMichael Niewöhner
Add interrupts for all enabled superio devices to quiet the warning about missing interrupts in devicetree. Vendor uses interrupt 0x00 for all devices except SUART* and KBC, so let's do that, too. This also changes SWC from 0x0b to 0x00. Verified with superiotool on X11SSM-F. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I7a6dc7345f020e53415a7d0d104ce93ab4b194fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/43886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonas Löffelholz Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-24mb/supermicro/x11-lga1151: Clean up gpio.hMaxim Polyakov
- remove comments (except the GPIO group), because it does not contain useful information that helps to understand the circuit, which we do not have; - remove empty lines between macros; - use a shorter PAD_CFG_GPI_INT() macro instead of PAD_CFG_GPI_TRIG_OWN() to set DRIVER mode. Change-Id: Ia7111341aab6f400da70d936849e4d4c9406905b Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-24supermicro/x11-lga1151/gpio: 4/4 Convert field macros to PAD_CFGMaxim Polyakov
Converts bit field macros to target PAD_CFG_*() macros, which were hidden in the comments. To do this, the following command was used: ./intelp2m -n -t 1 -p snr -file ../../src/mainboard/supermicro/ x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h ./intelp2m -n -t 1 -p snr -file ../../src/mainboard/supermicro/ x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h This is part of the patch set "mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m": CB:42916 - 1/4 Decode raw register values CB:42917 - 2/4 Exclude fields for PAD_CFG CB:42918 - 3/4 Fixes some field macro CB:35679 - 4/4 Convert field macros to PAD_CFG Tested with BUILD_TIMELESS=1, Supermicro X11SSH-TF and X11SSM-F, remains identical. Change-Id: Idad7536854d4b1ae7dcf7934e81de438478fe059 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35679 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24supermicro/x11-lga1151/gpio: 3/4 Fixes some field macroMaxim Polyakov
Fixes some bit fields to convert to target macros PAD_CFG_*() macros. This is part of the patch set "mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m": CB:42916 - 1/4 Decode raw register values CB:42917 - 2/4 Exclude fields for PAD_CFG CB:42918 - 3/4 Fixes some field macro CB:35679 - 4/4 Convert field macros to PAD_CFG Change-Id: I291f5f0f34505c466b610aa4049c8cc35937d140 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42918 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24supermicro/x11-lga1151/gpio: 2/4 Exclude fields for PAD_CFGMaxim Polyakov
This patch excludes bit fields that should be ignored [1] in order to convert current macros to target PAD_CFG_*() macros. The following commands were used for this: ./intelp2m -ii -fld cb -ign -t 1 -p snr -file ../../src/mainboard/ supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h /intelp2m -ii -fld cb -ign -t 1 -p snr -file ../../src/mainboard/ supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h [1] ignore RX Level/Edge Configuration (bit 26:25) and RX/TX Buffer Disable (bit 9:8) for the native function, because it does not affect the pad in this mode. This is part of the patch set "mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m": CB:42916 - 1/4 Decode raw register values CB:42917 - 2/4 Exclude fields for PAD_CFG CB:42918 - 3/4 Fixes some field macro CB:35679 - 4/4 Convert field macros to PAD_CFG Change-Id: Icdf366a8d416598cec5afcb9a0fae6bf7ecd7ba0 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42917 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24supermicro/x11-lga1151/gpio: 1/4 Decode raw register valuesMaxim Polyakov
Use the intelp2m utility [1,2] with -fld=cb options to convert the pad configuration format with the raw values of the DW0 and DW1 registers to the format with the bit fields macros: PAD_FUNC(), PAD_RESET(), PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc... Also use the -ii options to generate the target macro in the comments, so that it is easier to understand what result we should get: ./intelp2m -ii -fld cb -t 1 -p snr -file ../../src/mainboard/supermicro/ x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h ./intelp2m -ii -fld cb -t 1 -p snr -file ../../src/mainboard/supermicro/ x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h [1] https://github.com/maxpoliak/pch-pads-parser [2] https://review.coreboot.org/c/coreboot/+/35643 This is part of the patch set "mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m": CB:42916 - 1/4 Decode raw register values CB:42917 - 2/4 Exclude fields for PAD_CFG CB:42918 - 3/4 Fixes some field macro CB:35679 - 4/4 Convert field macros to PAD_CFG Tested with BUILD_TIMELESS=1, Supermicro X11SSH-TF and X11SSM-F, remains identical. Change-Id: I209ecdca75a0e62233d3726942c75ea06acc40a2 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42916 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10src/mb: Remove unneeded spaces before/after tabsElyes HAOUAS
Change-Id: I02979a0632a7b356985f96c3ba239daba178b4e3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39989 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-04mainboard/supermicro: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ie43c93c371073b4fe071b08522f351d0e20ed561 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-18mainboard/[^a-p]*: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I18e513cefc373b1cd70d31d1159928cc948a8476 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-02-25mb/supermicro/x11-lga1151-series: fix PNP warning for SUART1/2Michael Niewöhner
Fix PNP warning about missing devicetree entry for SUART1/2 by setting register 0xF0 to a sane (default) value. Change-Id: Ie852696aae09b9b03cebd6c3d8cbbd53a7138d89 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-02-25mb/supermicro/x11-lga1151-series: fix GPIO reset mappingMichael Niewöhner
When specifying _PAD_CFG_STRUCT with raw hex values, a logical reset value of 0x0 is only defined for GPD pads. For any other GPIOs this maps to 0x3. On the Supermicro X11 boards a value of 0x0 is set for GPP_D22 and GPP_F23, triggering the error "gpio_pad_reset_config_override: Logical to Chipset mapping not found". Set the right value (0x3<<30) for the affected GPIOs. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I3ae17dfc4d90f88f5b8bc5bee49740745778a91a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-02-14mainboard/supermicro: x11ssm-f: disable SUART3/4Michael Niewöhner
SUART3/4 are unused on this board (verified by checking registers on vendor BMC firmware). Further they break the console for an unknown reason. Thus disable them. Change-Id: I30bb8184d03ee1037d9ec33eb1d93ee540563fc5 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38818 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-23mb/supermicro/x11-lga1151-series: add x11ssm-f boardMichael Niewöhner
This adds another x11 series board, the X11SSM-F, which is similiar to X11SSH-TF but differs in PCIe interfaces/devices, GPIO settings and Ethernet interfaces. Change-Id: I24e6f0f41a844652f88b562285b26beef311a2c9 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Michael Niewöhner
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