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path: root/src/mainboard/supermicro/h8scm/mptable.c
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2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
2014-07-28AGESA boards: Use devicetree for PCI bus enumerationKyösti Mälkki
Previously MP table contained PCI_INT entries for PCI bus behind bridge 0:14.4 even if said PCI bridge function was disabled. Remove these as invalid, indeterminate bus number could cause conflicts. PCI_INT entries with bus_sb800[2], bus_hudson[2] and bus_yangtze[2] were invalid as there is no PCI bridge hardware on device 0:14.0. Remove these as invalid, indeterminate bus number could cause conflicts. Change-Id: Ie6a3807f64c8651cf9f732612e1aa7f376a3134f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6358 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-24AGESA: Drop offset on PCI device enumerationKyösti Mälkki
Integrated PCI devices in southbridge silicon have static BDFs, no need to have variables to store the parent bus or an offset with constant zero. Change-Id: I37d3794d36b5e5775da9215574ddc199696646d0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6333 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24AGESA fam15: Drop code that was commented outKyösti Mälkki
Only references to bus_rd890, bus_sp5100 and bus_sr5650 were in code sections that had been commented out. Change-Id: If5552c409ce948c494345f49dbaad790b398bff8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6331 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24AGESA fam15: Use local bus_isa storageKyösti Mälkki
Do not use a global as the value gets discarded anyway. Change-Id: I86aac304e073f0d74b011548d079e139891ec140 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6329 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-17AMD get_bus_conf(): Drop bus_type arrayKyösti Mälkki
Only ever used as lvalue, so no point creating the array. Change-Id: I6699dfae9377a895e9bc4a52579d00ddcfa60a9f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6277 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-07-03AGESA: Call get_bus_conf() just onceKyösti Mälkki
Instead of calling get_bus_conf() three times from write_tables() and executing it once, just make one call before entering write_tables(). Change-Id: I818e37128cb0fb5eaded3c1e00b6b146c1267647 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6133 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-04-20AMD AGESA cimx/sb700: Drop APIC_ID_OFFSET and MAX_PHYSICAL_CPUSKyösti Mälkki
Following boards use cimx/sb700: amd/dinar supermicro/h8qgi supermicro/h8scm tyan/s8226 Only amd/dinar had APIC_ID_OFFSET defined, thus all had 0x0. There was a nonsense preprocessor directive (MAX_CPUS * MAX_PHYSICAL_CPUS >= 1). Except for tyan, (MAX_CPUS * MAX_PHYSICAL_CPUS) % 256 == 0. Together with documented 4-bit restriction for APIC ID field, this APIC ID programming matches with MP tables and ACPI tables. I believe this would also fix cases of cimx/sb700 with MAX_CPUS<16, which we do not have in the tree. Change-Id: If8d65e95788ba02fc8d331a7af03a4d0d8cf5c69 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5539 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-28Supermicro H8SCM/H8QGI: Increase size of bus variable to meet APIBruce Griffith
Users of mptable_write_buses() pass two pass-by-reference parameters reflecting a maximum bus number and a search bus number. These bus numbers are expected to be held in "int" variables and are updated by the function. Both of the Supermicro boards define the search bus number as a byte value in mptable.c. For now, change the two Supermicro boards to use "int" to hold the search bus index. Change-Id: Ie71850719c1fa3cda0ac9c8773bb80650de95c70 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3546 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-30Supermicro h8scm: add agesa version of supermicroSiyuan Wang
Supermicro h8scm has a C32 CPU socket, the details of this board is: http://www.supermicro.com/Aplus/motherboard/Opteron4100/SR56x0/H8SCM-F.cfm We are planning to replace legacy C32 code with agesa and the h8scm_fam10 do not support family 15 CPU, so we update this mainboard with this patch. This code supports memory at 800M Hz of f10 CPU, bu f15 CPU does not has this limitation. If you want to change the frequency of memory, please edit the macros "BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT" and "BLDCFG_MEMORY_CLOCK_SELECT" in src/mainboard/supermicro/h8scm/buildOpts.c Change-Id: I9ca9e70d7f3e82c07e7d36695bf31008db152afb Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1510 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>