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2016-09-20src/mainboard/lenovo-winent: Add space around operatorsElyes HAOUAS
Change-Id: Iab2a879ebdea9d93ef5eb7e3abf875036c1e1cb4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16641 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-17mainboard: Clean up boot_option/reboot_bits in cmos.layoutNico Huber
Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector code) the reboot counter stored in `reboot_bits` isn't reset on a reboot with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR enabled, later stages (e.g. payload, OS) have to clear the counter too, when they want to switch to normal boot. So change the bits to (h)ex instead of (r)eserved. To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also remove all occurences of the obsolete `last_boot` bit that have sneaked in again since 24391321 (mainboard: Remove last_boot NVRAM option). Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/16157 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-14src/mainboard: Capitalize ROM, RAM, CPU and APICElyes HAOUAS
Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15987 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31sunw/ultra40m2: Fix handling non-existence of a devicePatrick Georgi
This probably never happens, but since we already test for the presence of the device, it makes no sense to try to configure it after its absense was determined. Change-Id: I9877dcd15819fb7949fa08a0954b05780df66316 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1347362 Reviewed-on: https://review.coreboot.org/15982 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-31mainboard: Format irq_tables.cPaul Menzel
Run the command below to format the files `irq_tables.c` of (mostly AMD) mainboards correctly with GNU indent 2.2.10. ``` $ git grep -l 'if (sum != pirq->checksum) {' | xargs indent -l ``` Fix up the following two checkpatch.pl errors manually. ``` ERROR: that open brace { should be on the previous line #1219: FILE: src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c:129: + uint8_t reg[8] = + { 0x41, 0x42, 0x43, 0x44, 0x60, 0x61, 0x62, 0x63 }; ERROR: that open brace { should be on the previous line #1221: FILE: src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c:131: + uint8_t irq[8] = + { 0x0A, 0X0B, 0X0, 0X0a, 0X0B, 0X05, 0X0, 0X07 }; ``` This is needed, so that follow-up commits, fixing checkpatch.pl errors and warnings, won’t run into conflicts with the git commit hooks, when for example, spaces instead of tabs are used for indentation. Change-Id: If254723f3013377fb3b9b08dd5eca6b76730ec4a Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/15932 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22lib: compile mdelay for romstagePatrick Georgi
Mimicking change I7037308d2, always compile mdelay for romstage. The boards that #included delay.c in the romstage now rely on the linker instead, which is a desirable cleanup. Change-Id: I7e5169ec94e5417536e967194e8eab67381e7c98 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13115 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-10mainboard/**/irq_tables.c: Remove reference to getpirPatrick Georgi
The obsolete and removed getpir utility remarked in its output that the data is autogenerated. The tool was removed because it wasn't very reliable, so there's no need to point that anymore. Change-Id: I5d624931ba7872b1fefa8fa3c270ae7367e069fa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/12354 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-10sunw/ultra40m2: initialize hardware monitor and fan controlJonathan A. Kollasch
Change-Id: I3fbb897feb68d899e5dec075a09d0dd605eca5ce Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/12309 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-10mainboard: Add Sun Ultra 40 M2 portJonathan A. Kollasch
The Ultra 40 M2 is a dual Socket F workstation with MCP55/IO55 chipset, DME1737 superio and onboard Firewire. This board port is for family 0Fh (K8) processors. Due to existing bugs, having memory on the second node will cause raminit to fail. Change-Id: I5b62ade908ffeb80e22f14edbe4c1ec04880bd30 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/12304 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-10mainboard: copy nvidia/l1_2pvv to sunw/ultra40m2 and renameJonathan A. Kollasch
Change-Id: Ia275a697caa73168553b5d588d54df651e0539d7 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/12303 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>