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2022-06-20mb/starlabs/labtop/cml: Organise USB ports by hardware portSean Rhodes
Group the USB ports by hardware ports, rather than separate USB 2.0 and 3.0 interfaces. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie9bc6b3e20dddeb14cea195ef9a719432f66c6e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20mb/starlabs/lite/glk: Configure LPC IO registersSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I47523fae8d1cb0fbb972a82c43a992c9fb606ed4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20mb/starlabs/lite/glkr: Configure LPC IO registersSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2d949af0086c231e27ac889c0aabd0d3e00c94fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/64984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-09mb/starlabs/lite: Disable Burst in Power Saver profileSean Rhodes
When the CMOS option `power_profile` is set to Power Saver, disable Burst. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4d9367306b3c0e83252cea3ee4c2733c8729d10c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-05-31mb/starlabs/lite/glk: Don't configure GPIO's 147 through 156Sean Rhodes
These are configured by the TXE, so they do not need to be configured. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia1bf4e32aa156a0e1a74df2f62eb31cdadb376a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-31mb/starlabs/lite/glk: Simplify GPIO macrosSean Rhodes
Use shorter macros to configure GPIOs. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I91961658dca0902080576134e63e6d8a7c78d711 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-31mb/starlabs/lite/glk: Disconnect unused GPIOsSean Rhodes
Disconnect GPIOs that are unused or not connected. Also, update comments that are vague or have errors. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic83797b8a8e05eed99db0356f360a329f6fbf347 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-31mb/starlabs/lite/{glk/glkr}: Configure prt0_gpioSean Rhodes
PERST_0 is not used, so set this to GPIO_PRT0_UDEF (undefined) to ensure that an undefined address is not added to GNVS. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iac9b116b2fa28824a89db28911188364dc9a1a53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-28mb/starlabs/lite/glk: Remove unnecessary DPTF UPDSean Rhodes
The default for DPTF is off (0), so remove the entry that sets this to off. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I0397ff6f71766a2f738ab2b71be298ef8f2b1c9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-05-28mb/starlabs/lite/{glk/glkr}: Remove unnecessary parametersSean Rhodes
Since using FSP 2.2.0.0, the defaults match the required settings so they no longer need to be specified. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie0e00cae67cb89b184392e97b8ec196d45ea5d91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-05-28mb/starlabs/labtop: Add LabTop Mk IIISean Rhodes
Tested using MrChromeBox's `uefipayload_202107` branch: * Windows 10 * Ubuntu 20.04 * MX Linux 19.4 * Manjaro 21 No known issues. https://starlabs.systems/pages/labtop-mk-iii-specification Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia52566e06f50c0abcfb657044538db8e92564c36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ben McMillen <ben@starlabs.systems>
2022-05-28mb/starlabs/lite: Add Bluetooth USB interfaceSean Rhodes
Enable the USB port that is used by the Bluetooth interface on the CNVI. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2a330618c5f1c5fd5e3147cb6307c157b28070ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/64545 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-28mb/starlabs/lite: Remove webcam USB port from devicetreeSean Rhodes
Remove the Webcam USB port form the devicetree and handle it solely in devtree, which will enable or disable it based on the CMOS option. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9c89c7103aca5c3d42215122e9d94c83947b6fee Reviewed-on: https://review.coreboot.org/c/coreboot/+/64544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-28mb/starlite/lite: Configure tcc_offset based on power_profile settingsSean Rhodes
Set tcc_offset value based on the power_profile value, ranging from 5 to 15 degrees. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id30bec9c095517884a7361226aed703b370f2207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-05-28mb/starlabs/lite/{glk/glkr}: Disable PMC PCI deviceSean Rhodes
The PMC is accessed via sideband registers, so the PCI device is not needed. Disabling it solves a bug where the laptop cannot be powered on without the charger connected. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I78f4aa4567dfc154ef5cb21f8746265259cd53e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64451 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-28mb/starlabs/lite/{glk/glkr}: Disable DPTF deviceSean Rhodes
DPTF is not used, so disable the corresponding PCI device. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9e4a3bada13dcabc1af3e1e5b3c215939f8239fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/64449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-05-28mb/starlabs/lite/{glk/glkr}: Remove subsystem device IDSean Rhodes
Remove the subsystem device ID for HDA devices, so that the correct Intel [8086:xxxx] is used. This was an old workaround for Windows that is no longer required with a new driver. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I63d6a4b0f19d400d683cab5dacca787d6c6a0fdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/64448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-05-28mb/starlabs/lite/{glk/glkr}: Decrease S3 assertion time to 28 msSean Rhodes
Set S3 assertion time to 28000us as this is sufficient time for rails to discharge. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4a14e7b30bb1fc4c0c1d3ff2f75069863458487f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64447 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-28mb/starlabs/lite/glkr: Correct OverCurrent PinSean Rhodes
The USB ports use both OC0 and OC1. Whilst they work perfectly with OC_SKIP, set them to the correct pins. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If173b443d9770083d76519b854b513d8e47b9e71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-28mb/starlabs/lite/glk: Correct OverCurrent PinSean Rhodes
The OC pin was set to 0, which isn't connected. All USB ports are connected to OC1. This solves a strange issue where the Lite can't be powered on without the charger connected. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I700ddde291f0e4be6e3787e2da13f6d3ece736b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-26soc/intel/tigerlake: Hook up FSP hyper-threading setting to option APIFelix Singer
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting from the FSP to the option API so that related mainboards don't have to do that. Unless otherwise configured (e.g. the CMOS setting or overriden by the mainboard code), the value from the Kconfig setting `FSP_HYPERTHREADING` is used. Also, remove related code from the mainboard starlabs/laptop/tgl, since it is obsolete now. Change-Id: I49bbd4a776b4e6c55cb373bbf88a3ca076342e3e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-05-26soc/intel/cannonlake: Hook up FSP hyper-threading setting to option APIFelix Singer
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting from the FSP to the option API so that related mainboards don't have to do that. Unless otherwise configured (e.g. the CMOS setting or overriden by the mainboard code), the value from the Kconfig setting `FSP_HYPERTHREADING` is used. Also, remove related code from the following mainboards, since it is obsolete now. * siemens/chili * starlabs/laptop/cml Change-Id: I173b87da5ce76549672c50ba30204cd77be8b82f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-05-21mb/starlabs/lite/glk: Correct indendation in devicetreeSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I780e2765059ad7473fe5f33c50dd0d8a561151fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/64390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-12mb/starlabs/labtop: Enable Max Charge for CMLSean Rhodes
Enable the max charge feature for cml, as the EC supports it since Star Labs EC firmware 1.06. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I779a686960b63025fb5f40e826ed117f402a0b2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64093 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-06mb/starlabs/lite: Change PMC from hidden to onStephen Edworthy
With the PMC set to hidden, on certain Operating Systems, including ZorinOS 16 and Manjaro 21.2.5, it would get stuck at a black screen when exiting from S3. With the PMC set to on, this issue no longer occurs. Signed-off-by: Stephen Edworthy <stephen@starlabs.systems> Change-Id: I0cf1be7f6919d974614f2196a0eb611cc40abe3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-04-21tpm: Refactor TPM Kconfig dimensionsJes B. Klinke
Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-06mb/starlabs/labtop: Remove subsystem device IDSean Rhodes
Remove the subsystem device ID for HDA devices, so that the correct Intel [8086:xxxx] is used. This was an old workaround for Windows that is no longer required with a new driver. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I50c03a2df06af3ef1939afd0739e083a9056557f Reviewed-on: https://review.coreboot.org/c/coreboot/+/63348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-04mb/starlabs/lite: Add Lite Mk IV variantSean Rhodes
Tested using upstream edk2: * Windows 10 * Ubuntu 20.04 * MX Linux 19.4 * Manjaro 21 No known issues. https://starlabs.systems/pages/starlite-specification Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id1cf2846a139004e9bec7bb27e9afe07b7e6f64f Reviewed-on: https://review.coreboot.org/c/coreboot/+/62706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-01mb/starlabs/labtop: Disable legacy_8254_timer by defaultSean Rhodes
It was enabled due to known compatibility issues with Qubes OS. Since the release of R4.1.0, this issue is no longer present so it can be disabled. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iab6048dc93112b9365f0c2b46225569073eb32f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-04-01mb/starlabs/laptop: Enable rtd3 for SSD on TGLStephen Edworthy
Enabling rtd3 reduces power consumption when the SSD is idle. Tested and verified on the StarBook Mk V (TGL), using PowerTop on Manjaro 21.2.5 GNOME at 20% Brightness. Signed-off-by: Stephen Edworthy <stephen@starlabs.systems> Change-Id: I0d8aa185a322bb8d1aba51ccaab03c521cec2770 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-04-01mb/starlabs/labtop: Add CMOS defaults for EC functionsSean Rhodes
Set the CMOS defaults for EC related functions: * Function Lock = Enabled * Trackpad = Enabled * Keyboard Backlight Brightness = Off * Keyboard Backlight State = Enabled Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I528c30893d2af87584a09f23b982b5f36b37a873 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-30mb/starlabs/lite: Move Verb Table to variant directorySean Rhodes
Move the verb table to variant directory to allow for different tables for different variants. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4260188057d1c3b4e6ea7c82f085fad0cc244881 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-30ec/starlabs/merlin: Make EC function names genericSean Rhodes
Rather than using `ite_`, use `ec_` so the same functions can be called for different ECs. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie61af233f731eb47772af1c82c6abdc515bc89cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/62700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-29src/mainboard/starlabs: Remove unused <option.h>Elyes Haouas
Found using: diff <(git grep -l '#include <option.h>' -- src/) <(git grep -l 'sanitize_cmos(\|get_uint_option(\|set_uint_option(\|get_uint_option(\|set_uint_option' -- src/) |grep "<" Change-Id: Ib79dfa73b8a30ae1b1e432318bd42e4e3d845af3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-03-15soc/intel/tgl: move DIMM_SPD_SIZE from mb to SoC KconfigMichael Niewöhner
All TGL mainboards are setting DIMM_SPD_SIZE to 512. Thus, default to 512 in the SoC Kconfig and drop it from the mainboard Kconfigs. Change-Id: I9fd947b61c984e10bd5fba20b73280b08623a008 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62766 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-15{mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototypeSubrata Banik
This patch modifies `memcfg_init` and `variant_memory_init`functions argument from FSP_M_CONFIG to FSPM_UPD. This change in `memcfg_init()` argument will help to update the architectural FSP-M UPDs from common code blocks rather than going into SoC and/or mainboard implementation. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-14mb/starlabs/labtop: Pull SSD Pin to low when entering S3Sean Rhodes
Pull GPP_D16 to low when suspending, otherwise it will remain active and use power. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2cbe7caf66e8d8c27414aca3b74416c2b8115ea1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-10mb/starlabs/labtop: Remove unnecessary return value from MWAKSean Rhodes
Don't return 0x00 when running MWAK as it is not needed. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic62eab8ae5319aff37c61fc29d701d9a36ada919 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-10mb/starlabs/labtop: Always run PTSSean Rhodes
Remove the dependency on Arg0 so PTS always runs. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I96c44397d62848231039330a32de781f75bb56bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
2022-03-09mb/starlabs/labtop: Remove duplicate value from KconfigSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I0324747f936be27ee39e586124005530d5c424b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-08ec/starlabs: Guard Max Charge in KconfigSean Rhodes
Guard Max Charge EC write in Kconfig so it's only used on platforms that support it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7be39cd9543c8253d53070950edc6908a21e864a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-08mb/starlabs/labtop: Add LabTop Mk IVSean Rhodes
Tested using MrChromeBox's `uefipayload_202107` branch: * Windows 10 * Ubuntu 20.04 * MX Linux 19.4 * Manjaro 21 No known issues. https://starlabs.systems/pages/labtop-mk-iv-specification Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Idbaa907dc38dc521961806132f21b7a90324ec9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58428 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-01mb/starlabs/lite: Add StarLite Mk IIISean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iddbf2022d03735d6a0e6d098c21643f5fdc875f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-22mb/starlabs/labtop: Reconfigure GPIOsSean Rhodes
Reconfigure the GPIO's so that they are configured correctly. The original configuration was based on the AMI firmware, and whilst it worked, it wasn't optimal. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I27ecf066685f2a81ac884a9f276c518544449443 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-22mb/starlabs/labtop: Reconfigure CNVi GPIOsSean Rhodes
Reconfigure the CNVi GPIO's so that they are configured correctly. The original configuration was based on the AMI firmware, and whilst it worked, it wasn't optimal. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9fc9963e91da0267c8740fee20a3ec41895b4953 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-22mb/starlabs/labtop: Update trackpad GPIO configurationSean Rhodes
Update trackpad GPIO to avoid IRQ Storm, that causes high power consumption when idling or in S3. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ieee27bd9079617ab95f4f1e27ef98b49e89e5b41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-22mb/starlabs/labtop: Configure TPM_IRQ GPIO for TGLSean Rhodes
Configure the TPM IRQ GPIO for TGL (StarBook Mk V) so that the hardware TPM can be used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ife88075e70184b46e69f2e24c70b85ec254edd64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60756 Reviewed-by: Andy Pont <andy.pont@sdcsystems.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-22mb/starlabs/labtop: Don't configure ESPI GPIOsSean Rhodes
Don't configure ESPI GPIOs as the default values are correct. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I052fbfccd075d19340d3e27ad0c62965c80badaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/60755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth - Personal <martinroth@google.com>
2022-02-22payloads/tianocore: Rework MakefileSean Rhodes
Rework edkii makefile so that the various build options are unified between CorebootPayloadPkg, uefipayload_202107 and upstream. This sets the project directory based on the git repository name i.e. https://github.com/mrchromebox/edk2 becomes mrchomebox Also builds to $(obj)/UEFIPAYLOAD.fd and allows using a commit ID without a branch. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3cc274e7385dd71c2aae315162cc48444b7eaa5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Martin Roth - Personal <martinroth@google.com>
2022-02-15mb/starlabs/labtop: Disconnect unused GPIO'sSean Rhodes
Disconnect all GPIO's that aren't connected to anything. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2050da62f73c0f99fbfef013c22e35225cc480c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-15mb/starlabs/labtop: Add comments for GPIOsSean Rhodes
Add comment for each GPIO details its endpoint based on the schematic. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia3678274dcd52285019fb3cf8ccd22617268ce1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/60123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-01-14soc/intel/tgl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4a81fd58df468e2711108a3243bf116e02986316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-14soc/intel/tigerlake: add devicetree option PcieRpSlotImplementedMichael Niewöhner
Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI bit set for any slots of already existing boards, add set the option PcieRpSlotImplemented=1 where appropriate. Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-10src/mainboard/{siemens,starlabs}: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: I9116965512a5b3241fd7e28537d96637008b31e4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-05mb/starlabs/labtop: Remove display from devicetreeSean Rhodes
Remove display from devicetree as Intel's brightness controls are not used on this platform. This solves the below errors appearing in dmesg: No Local Variables are initialized for Method [_BCL] No Arguments are initialized for method [_BCL] Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Icf2f2fa33abd11952c888c9502d1d5ef1ad6544f Reviewed-on: https://review.coreboot.org/c/coreboot/+/59258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-05mb/starlabs/labtop: Replace leading whitespace with tabSubrata Banik
Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4d7324148ba182d0317b1f64e39f04a8a55fe79b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sean Rhodes <admin@starlabs.systems> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-04mb/starlabs/labtop: Enable I2C4Sean Rhodes
Enable unused I2C4 PCI device (00:19.0) so that UART2 (00:19.2) can be enumerated properly, using `PchSerialIoSkipInit` to prevent FSP-S from configuring anything regarding I2C4 (e.g. GPIOs). Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9c2c4f67672ba5667ebdae9ecc01054449dd3dfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/60264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-04starlabs: Convert EC_GPE_SCI to KconfigSean Rhodes
Convert EC_GPI_SCI to Kconfig option with default value of 0x50 that is used by most boards. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8d47ebe76394fe1bcb217e0c6211db1566f82189 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-01src: Drop duplicated includesElyes HAOUAS
<types.h> already provides <commonlib/bsd/cb_err.h>, <limits.h>, <stdbool.h>, <stdint.h> and <stddef.h> headers. Change-Id: I700b3f0e864ecce3f8b3b66f3bf6c8f1040acee1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-12-23mb: Remove dot from end of non-sentence commentPaul Menzel
Run the command below to fix all occurrences. $ git grep -l 'configuration in bootblock\. \*/' | xargs sed -i 's,configuration in bootblock\. \*/,configuration in bootblock */,' Change-Id: I84669341e2c8976953284dbaf113da3397857de3 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-23mb/starlabs/labtop: Update VBTSean Rhodes
Using Vbt.bin version 244, with the following changes: * Add 200ms delay to sink (T3) to avoid no response to AUX Channel transaction, which manifests as a repeating, colourful flicker. * Increase maximum supported refresh rate to 120Hz Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ifc03b8f5d45cbbf90fb61d8b08148ed402dd85ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/59727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
2021-12-20mb/starlabs/labtop: Add enum for `power_profile`Angel Pons
Introduce and use an enum for the `power_profile` CMOS option. Add a helper function that converts CMOS values into enum values. Using an enum allows GCC to warn about switch statements using enum types for their control expressions not handling all possible enum values, and also improves readability. Change-Id: I47a453ea12d164d26908a9944a89a481757e753c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <admin@starlabs.systems> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-20mb/starlabs/labtop: Rename some filesAngel Pons
Rename `mainboard.c` to `smbios.c` as it only contains SMBIOS functions. Rename `ramstage.c` to `mainboard.c` as it contains the mainboard chip operations struct. Change-Id: I9548ca72a7583de98f5b154e3381825bba00d5cf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <admin@starlabs.systems> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-19mainboard: Fix comment about early GPIOsAngel Pons
These boards program the early GPIO table in bootblock, not romstage. Change-Id: Iae9353d106483f30cefa2d035d96e63e4c127261 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Sean Rhodes <admin@starlabs.systems> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-15mainboard/starlabs/labtop: Hook up Thunderbolt to CMOSSean Rhodes
Hook up Thunderbolt and related settings to CMOS value of `thunderbolt`. Changes TcssXhciEn, UsbTcPortEn and the relevant PCI devices. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ibadc7464831242ae51982610b410ccf0a6811edd Reviewed-on: https://review.coreboot.org/c/coreboot/+/59705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
2021-12-09soc/intel/tigerlake: Hook up DPTF device to devicetreeFelix Singer
Hook up `Device4Enable` FSP setting to devicetree state and drop its redundant devicetree setting `Device4Enable`. The following mainboards enable the DPTF device in the devicetree despite `Device4Enable` is not being set. * google/deltaur Thus, set it to off to keep the current state unchanged. Change-Id: Ic7636fc4f63d4beab92e742a6882ac55af2565bc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09mb/starlabs/labtop: Enable SMBus in Device TreeSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8bc3025331bb25b02712b5d2b654f7997f0aba4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/59926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-12-09soc/intel/tigerlake: Hook up SMBus device to devicetreeFelix Singer
Hook up `SmbusEnable` FSP setting to devicetree state and drop its redundant devicetree setting `SmbusEnable`. The following mainboards enable the SMBus device in the devicetree despite `SmbusEnable` is not being set. * google/deltaur * starlabs/laptop Thus, set it to off to keep the current state unchanged. Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22mainboard/starlabs: Add StarBook Mk VSean Rhodes
Tested using MrChromeBox's `uefipayload_202107` branch: * Windows 10 * Ubuntu 20.04 * MX Linux 19.4 * Manjaro 21 No known issues. https://starlabs.systems/pages/starbook-specification Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I090971a9e8d2be5b08be886d00d304607304b645 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56088 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04Revert "src/mainboard: Add Star Labs labtop series"Tim Wawrzynczak
This reverts commit 2e665eb8daa2963c52092e694a5316dc544a23f5. Reason for revert: Was submitted too early and out-of-order. Change-Id: I119b7a81b849bbe3424d73d5fdf9b55481444686 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54971 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04src/mainboard: Add Star Labs labtop seriesSean Rhodes
Add support for LabTop Mk III (kblr) and LabTop Mk IV (cml) Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iffa6061b0e600880b0c93746f35b1731e4841e31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 12:09:58 +0000