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Commit 9bbc039c457774dbeb44ea37ecc6507144d49b61 ("soc/intel/skylake:
Hook up FSP hyper-threading setting to option API") already hooks up
the `hyper_threading` CMOS option in SoC code, so there's no need to
do it from mainboard code.
Change-Id: I602452266a8465cced12454f800ea023f382ba6f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69522
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable the mirror flag for CML and TGL.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I51678bdb8d876d238076e12c6315a53c5da59628
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Replace the string with a Kconfig option
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib11ddd04c44f47b94f4fc9eaed278d554d581b0f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is no longer needed so remove it.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I82841c2114ceb5e7a46ce228fce63d24822098d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68084
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure PMC mux in devicetree.
Tested on StarBook Mk V with Ubuntu 22.04.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I297d5446e43357d97357f345668cf40dcd28502d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68083
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Enable the P2SB so that the SPI is discoverable by the OS.
Change-Id: I49802f93a97a18ecc10f48d213619855728e1290
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67029
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ie9655406c7afe7a22f131d35633a697c5bbde4e3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2da15db3d7fba4396c74800e531476c108cafe17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67421
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable SRAM in devicetree so that resources are allocated properly
for it.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1d7ee4f950b31f2be6fb7bd107b5fe54785ed81a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67420
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable the P2SB so that the SPI is discoverable by the OS.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ied7a6ea706e6da86182c109ab4813fa3fcebb1f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67419
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add variant specific cmos files, which avoid options like "Thunderbolt"
existing in platforms that don't support such options.
This change also removes entries that were never used, including:
* smi_handler
* usb_always_on
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I359e5c5bbf29eb474f2d3bc42a8e80afc0a5d38a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Previously, the Bluetooth interface worked when port 9 was enabled.
Now, it works with port 5 enabled, which matches the schematic.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If783e60c8120adcd6522676cb3343ed46bf39d78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Tidy up the layout to remove unnecessary sizes. This change also makes
the flash start at 0x0 and increases the size of the FMAP to 0x1000.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I46663003857eb50271c6ad1da6c4e56c8f4bb6c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Historically, ChromeOS devices have worked around the problem of OEMs
using several different parts for touchpads/touchscreens by using a
ChromeOS kernel-specific 'probed' flag (rejected by the upstream kernel)
to indicate that the device may or may not be present, and that the
driver should probe to confirm device presence.
Since c636142b, coreboot now supports detection for i2c devices at
runtime when creating the device entries for the ACPI/SSDT tables,
rendering the 'probed' flag obsolete for touchpads. Switch all touchpads
in the tree from using the 'probed' flag to the 'detect' flag.
Touchscreens require more involved power sequencing, which will be done
at some future time, after which they will switch over as well.
TEST: build/boot at least one variant for each baseboard in the tree.
Verify touchpad works under Linux and Windows. Verify only a single
touchpad device is present in the ACPI tables.
Change-Id: I47c6eed37eb34c044e27963532e544d3940a7c15
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67305
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Disable INTEL_LPSS_UART_FOR_CONSOLE to stop debug output on UART 2.
This decreases boot time on all boards by around 60%.
TGL before:
Total Time: 10,110,807
TGL after:
Total Time: 3,851,641
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8f8d5cd46e87e7dafe0669b4a29c872b1789eb60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The ALC269 does not support the hardware equaliser, so remove the
entries related to this, as they have no effect.
Revert to the ALC269 defaults which work correctly with Linux. This
also corrects the subsystem id from 0x10ec111e to 0x10ec10d0.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I82647f67730ec344591f7dbd759a421c116d4fdd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I251840b409dead62586cefe5856b6c544401ba30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Enable CRB_TPM to allow the use of the fTPM (Intel PTT).
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I7b69854ea636947480402ce12450f431028660a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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coreboot uses TianoCore interchangeably with EDK II, and whilst the
meaning is generally clear, it's not the payload it uses. EDK II is
commonly written as edk2.
coreboot builds edk2 directly from the edk2 repository. Whilst it
can build some components from edk2-platforms, the target is still
edk2.
[1] tianocore.org - "Welcome to TianoCore, the community supporting"
[2] tianocore.org - "EDK II is a modern, feature-rich, cross-platform
firmware development environment for the UEFI and UEFI Platform
Initialization (PI) specifications."
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4de125d92ae38ff8dfd0c4c06806c2d2921945ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65820
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The LabTop was renamed to StarBook since the release of the Mk V.
This change keeps the directory name more relevant, as there are
more boards using the name StarBook.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3513fb56c1adf663ed7bcdade2cc52cd8c0d6f4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65640
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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