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path: root/src/mainboard/starlabs/lite
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2023-08-10mb/starlabs/lite/glkr: Disable PSRSean Rhodes
Disable PSR in the VBT to avoid flickering on kernels later than 5.15. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3640fcea73e278e6c8968a4b0c9ba7cf04a2361f Reviewed-on: https://review.coreboot.org/c/coreboot/+/77134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-08-10mb/starlabs/lite/glk: Disable PSRSean Rhodes
Disable PSR in the VBT to avoid flickering on kernels later than 5.15. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5b58f4d26fa0032a5aed3af0db71a5daf41fdd8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/76941 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-06mainboard/starlabs/*: Remove the power_on_after_fail optionSean Rhodes
None of these boards have an RTC battery, so this option has no effect. Remove it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9a55227f74c0b9ae9b56bdef4b8f53b2425b331c Reviewed-on: https://review.coreboot.org/c/coreboot/+/75450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-19soc/intel/apollolake: Switch to snake case for ModPhyIfValueMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'ModPhyIfValue'. Change-Id: I4cdf68e65cea4ab316af969cd6a8d096b456518d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75855 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/intel/apollolake: Switch to snake case for DisableComplianceModeMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'DisableComplianceMode'. Change-Id: I9d5605134a753f161a66857c7f78844ae7490cd6 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-02soc/intel/apollolake: Switch to snake case for SataPortsEnableMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'SataPortsEnable'. Change-Id: I0df35125360eb42a03d5445011d72842cb2b8d7e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75553 Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-04-04mb/starlabs/*: Add CMOS entries for the mirror flagSean Rhodes
Add the required CMOS entries for the mirror flag, so that it can be enabled from a defconfig. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I174ac896df050480ee90c8141c5536b628c98432 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73682 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-04Revert "mb/starlabs/*: Remove sleepstates.asl"Sean Rhodes
This reverts commit ac69ce91229dee68d4135c596f49cf9e5efbe1e9. Reason for revert: Removing breaks suspend in kernels > 6.2 and Windows. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3e90266e66192b328b9af51c5e614774a248ddf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
2023-03-26mb/starlabs/*: Remove sleepstates.aslSean Rhodes
Remove the sleepstates.asl as it was written for SOCs pre-Skylake and not needed. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I46fe934c2a50b3d61575f66f0881ab6754fe8dc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-02-19treewide: Remove useless "_STA: Status" commentElyes Haouas
Change-Id: I99ded00fa6dadb494c1523d00063dbc1fde95614 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73093 Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-17treewide: Remove unuseful "_UID: Unique ID" commentElyes Haouas
Change-Id: I150a4ed94bcaead6eb45f1c4b4952ae6957e0940 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_CID: Compatible ID" commentElyes Haouas
Change-Id: I7db69e2faf412b9c6732f6dfc362d5774094ef27 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_HID: Hardware ID" commentElyes Haouas
Change-Id: I5eb1424e9e6c1fbf20cd0bf68fbb52e1ec97f905 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-03soc/intel/apl: Move cpu cluster to chipset.cbArthur Heymans
Change-Id: I7eaf625e5acfcefdae7c81e186de36b42c06ee67 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-01-30mb/*: Remove lapic from devicetreeArthur Heymans
The parallel mp code picks up lapics at runtime, so remove it from all devicetrees that use this codebase. Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-07mb/starlabs: Remove the bios_version functionSean Rhodes
Remove smbios_mainboard_bios_version so that the default CONFIG_LOCALVERSION can be used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia94f8683a54a98f4e3b1f51521db7e3ccb56ba48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-12-27mainboard/acpi: Replace constant "One" with actual numberFelix Singer
Change-Id: Id1078b14a805eea53d2a7c5a8183a5413f26e115 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71521 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22mb/starlabs/*: Bind console serial output to EDK2_DEBUGSean Rhodes
Configure the UART port but only enable UART debug for EDK2 debug builds. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I54e1dc5768fd765254c7ede91eaa45842fed3bd6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69322 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-06mb/starlabs/lite/{glk,glkr}: Adjust THERMTRIP GPIOSean Rhodes
Modify the configuration of GPIO_74 (PMIC Thermal Trip Point) as in it's current configuration, it stops the laptop entering S5. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I0e31f095ff42a03e3ea1496fe67d69b0f1763a3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/67418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-10-29mb/starlabs/*: Change the local version to KconfigSean Rhodes
Replace the string with a Kconfig option Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib11ddd04c44f47b94f4fc9eaed278d554d581b0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-15mb/starlabs/lite/{glk,glkr}: Enable PMCSean Rhodes
Enable PMC in devicetree so that resources are allocated properly for it. Tested on StarLite Mk III & IV, and both can power on correctly. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib4384b55751a9979e470dd04f6814d4ca170ff34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67409 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-15mb/starlabs/lite: Reset XHCI before entering S5Sean Rhodes
Reset the XHCI controller prior to S5 to avoid XHCI preventing shutdown. Linux needs to put the XHCI into D3 before shutting down but the powerstate commands do not perform a reset. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3be70443eb85a7dff8055c9de0ca2fd89f4fc88d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67678 Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-06mb/starlabs/lite/glkr: Enable configuring Fast Charging on the Lite Mk IVSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I714867d455c4e0d01d6cb1cb9dc64669fb41100c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-06mb/starlabs/lite: Add variant specific cmos.layout and cmos.defaultSean Rhodes
Add variant specific cmos files, which avoid options like "FastCharge" existing in platforms that don't support such options. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I04264cf72d47ef719acfd144d8bf9acb0ceccc11 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-08mb/starlabs/lite/{glk,glkr}: Enable SRAMSean Rhodes
Enable SRAM in devicetree so that resources are allocated properly for it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ibdd2ee455f5bf6cd95bba6bab8689da664bfcf54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-08-24mb/starlabs/lite: Enable P2SBSean Rhodes
Enable the P2SB so that the SPI is discoverable by the OS. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9c12161d4868deae5b8900cfa2f42517a9f0b7e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-21mb/starlabs/*: Disable INTEL_LPSS_UART_FOR_CONSOLESean Rhodes
Disable INTEL_LPSS_UART_FOR_CONSOLE to stop debug output on UART 2. This decreases boot time on all boards by around 60%. TGL before: Total Time: 10,110,807 TGL after: Total Time: 3,851,641 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8f8d5cd46e87e7dafe0669b4a29c872b1789eb60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-19mb/starlabs/lite/glkr: Remove old comment from devicetreeSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib203451bb3da06efd1d3f6e48496b370d81f4b7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66196 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-19mb/starlabs/lite: Use chipset.cb aliasesSean Rhodes
GLKs chipset configures the devices, so use these aliases and remove the entries when they are identical. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic29e5305346c3b7fbf66b027754a9ddd16b16269 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66195 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-13payloads/tianocore: Rename TianoCore to edk2Sean Rhodes
coreboot uses TianoCore interchangeably with EDK II, and whilst the meaning is generally clear, it's not the payload it uses. EDK II is commonly written as edk2. coreboot builds edk2 directly from the edk2 repository. Whilst it can build some components from edk2-platforms, the target is still edk2. [1] tianocore.org - "Welcome to TianoCore, the community supporting" [2] tianocore.org - "EDK II is a modern, feature-rich, cross-platform firmware development environment for the UEFI and UEFI Platform Initialization (PI) specifications." Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4de125d92ae38ff8dfd0c4c06806c2d2921945ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/65820 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-25mb/starlabs/lite: Add support for VBOOTSean Rhodes
Add the required files to support VBOOT for when it is enabled. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I083107b21c23f42193fc88aa174ec22850f45bc8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65705 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-07-22mb/starlabs/lite: Simplify the flash layoutSean Rhodes
Remove the sections that coreboot doesn't need to know about. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ide6c0d44f1f9ad9b962d2b8e14ac91e87f5ca031 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65453 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-13mb/starlabs/lite/{glk/glkr}: Remove Bluetooth USB portSean Rhodes
This reverts commit 0225af3c2ba661de82e15f163258605917ca28cf as it has no effect as the USB interface is configured by FSP S. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I20ca355eb1e088d7a7c8eacbc888ffc90833194b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-07-05mb/starlabs/lite/glk: Update VbtSean Rhodes
Update the Vbt to disable the fixed mode feature, to allow for bootloader resolutions higher than 1920x1080. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ibd9850dcaef97a58c6694ee594014e9f16ae7f96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-06-22mb/starlabs/lite/{glk/glkr}: Disable UFS deviceSean Rhodes
Disable 1d.0 UFS as it is not used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib392bc64db440ea3d98ee62536d5395587a3f6aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-06-21mb/starlabs/lite/{glk/glkr}: Disable Sata Port 1Sean Rhodes
Disable Sata Port 1 as it is not used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I93ecdaba5d1ce96ddcf3695edd7fb109054743e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-06-21mb/starlabs/lite/glkr: Don't configure GPIO's 147 through 156Sean Rhodes
These are configured by the TXE, so they do not need to be configured. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I13957992d637a53203b4328e39c0e6607e017891 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-21mb/starlabs/lite/glkr: Simplify GPIO macro'sSean Rhodes
Use shorter macro's to conifgure GPIO's. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I926aac8679f847cd963be07786e9fe2e4c63bda6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-21mb/starlabs/lite/glkr: Disconnect unused GPIO'sSean Rhodes
Disconnect GPIO's that are unused, or not connected. Also update comments that are vague or have errors. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1b071ec1d194f76ee78066396bac8dfff5ec851b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64651 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-20soc/intel/apollolake: Hook Up SataPortEnable to devicetreeSean Rhodes
Hook Up SataPortsEnable to the devicetree. As the default value is 0, set both [0] and [1] in all mainboards so they aren't affected. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ica8cf9484a6e6fe4362eabb8a9a59fcaf97c1bd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64524 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-20mb/starlabs/lite/glk: Organise USB ports by hardware portSean Rhodes
Group the USB ports by hardware ports, rather than separate USB 2.0 and 3.0 interfaces. This change also corrects the daughterboard USB 3.0 port number. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib6a934a1e5e65fe387c63b78cbe80e45e97e0a8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64796 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-20mb/starlabs/lite/glkr: Correct the daughterboard USB 3.0 port numberSean Rhodes
The daughterboard USB 3.0 was set to port 3, which is incorrect. This patch corrects that to port 4. This fixes an issue where USB 3.0 devices are not detected when plugged in to this port. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I50f86dee1b512d0dd20d07e3ee17ebfa5e537bc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20mb/starlabs/lite/glkr: Correct USB port numbersSean Rhodes
The USB ports for the Motherboard USB 3.0 and Type-C were labelled incorrectly. This change swaps the ports, so they are labelled correctly and also corrects the over-current pins that they use. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I80484dc8bdd68dd72b3848720c790d59237a9f8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20mb/starlabs/lite/glkr: Organise USB ports by hardware portSean Rhodes
Group the USB ports by hardware ports, rather than separate USB 2.0 and 3.0 interfaces. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2a7f50ca2b2001e83211e8eba56bfa929ecdfd74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20mb/starlabs/lite: Enable enhanced C-statesSean Rhodes
Tested on the StarLite Mk III & Mk IV with Zorin 16.2 Core. This resulted in a reduction in power consumption of approximately 3%. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7b5f4e01bc786db02184b722c74fda7d0ca055be Reviewed-on: https://review.coreboot.org/c/coreboot/+/64709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20mb/starlabs/lite: Configure MMIO window for ECSean Rhodes
The Nuvoton EC requires a window to be opened for updates, so open this window only if the Nuvoton EC is present. Change-Id: Iaa45aa58749c4d0bfc77e60b52eab2bcb270f3ee Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20mb/starlabs/lite/glk: Configure LPC IO registersSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I47523fae8d1cb0fbb972a82c43a992c9fb606ed4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20mb/starlabs/lite/glkr: Configure LPC IO registersSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2d949af0086c231e27ac889c0aabd0d3e00c94fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/64984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-09mb/starlabs/lite: Disable Burst in Power Saver profileSean Rhodes
When the CMOS option `power_profile` is set to Power Saver, disable Burst. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4d9367306b3c0e83252cea3ee4c2733c8729d10c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-05-31mb/starlabs/lite/glk: Don't configure GPIO's 147 through 156Sean Rhodes
These are configured by the TXE, so they do not need to be configured. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia1bf4e32aa156a0e1a74df2f62eb31cdadb376a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-31mb/starlabs/lite/glk: Simplify GPIO macrosSean Rhodes
Use shorter macros to configure GPIOs. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I91961658dca0902080576134e63e6d8a7c78d711 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-31mb/starlabs/lite/glk: Disconnect unused GPIOsSean Rhodes
Disconnect GPIOs that are unused or not connected. Also, update comments that are vague or have errors. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic83797b8a8e05eed99db0356f360a329f6fbf347 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-31mb/starlabs/lite/{glk/glkr}: Configure prt0_gpioSean Rhodes
PERST_0 is not used, so set this to GPIO_PRT0_UDEF (undefined) to ensure that an undefined address is not added to GNVS. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iac9b116b2fa28824a89db28911188364dc9a1a53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-28mb/starlabs/lite/glk: Remove unnecessary DPTF UPDSean Rhodes
The default for DPTF is off (0), so remove the entry that sets this to off. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I0397ff6f71766a2f738ab2b71be298ef8f2b1c9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-05-28mb/starlabs/lite/{glk/glkr}: Remove unnecessary parametersSean Rhodes
Since using FSP 2.2.0.0, the defaults match the required settings so they no longer need to be specified. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie0e00cae67cb89b184392e97b8ec196d45ea5d91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-05-28mb/starlabs/lite: Add Bluetooth USB interfaceSean Rhodes
Enable the USB port that is used by the Bluetooth interface on the CNVI. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2a330618c5f1c5fd5e3147cb6307c157b28070ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/64545 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-28mb/starlabs/lite: Remove webcam USB port from devicetreeSean Rhodes
Remove the Webcam USB port form the devicetree and handle it solely in devtree, which will enable or disable it based on the CMOS option. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9c89c7103aca5c3d42215122e9d94c83947b6fee Reviewed-on: https://review.coreboot.org/c/coreboot/+/64544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-28mb/starlite/lite: Configure tcc_offset based on power_profile settingsSean Rhodes
Set tcc_offset value based on the power_profile value, ranging from 5 to 15 degrees. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id30bec9c095517884a7361226aed703b370f2207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-05-28mb/starlabs/lite/{glk/glkr}: Disable PMC PCI deviceSean Rhodes
The PMC is accessed via sideband registers, so the PCI device is not needed. Disabling it solves a bug where the laptop cannot be powered on without the charger connected. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I78f4aa4567dfc154ef5cb21f8746265259cd53e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64451 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-28mb/starlabs/lite/{glk/glkr}: Disable DPTF deviceSean Rhodes
DPTF is not used, so disable the corresponding PCI device. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9e4a3bada13dcabc1af3e1e5b3c215939f8239fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/64449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-05-28mb/starlabs/lite/{glk/glkr}: Remove subsystem device IDSean Rhodes
Remove the subsystem device ID for HDA devices, so that the correct Intel [8086:xxxx] is used. This was an old workaround for Windows that is no longer required with a new driver. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I63d6a4b0f19d400d683cab5dacca787d6c6a0fdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/64448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-05-28mb/starlabs/lite/{glk/glkr}: Decrease S3 assertion time to 28 msSean Rhodes
Set S3 assertion time to 28000us as this is sufficient time for rails to discharge. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4a14e7b30bb1fc4c0c1d3ff2f75069863458487f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64447 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-28mb/starlabs/lite/glkr: Correct OverCurrent PinSean Rhodes
The USB ports use both OC0 and OC1. Whilst they work perfectly with OC_SKIP, set them to the correct pins. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If173b443d9770083d76519b854b513d8e47b9e71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-28mb/starlabs/lite/glk: Correct OverCurrent PinSean Rhodes
The OC pin was set to 0, which isn't connected. All USB ports are connected to OC1. This solves a strange issue where the Lite can't be powered on without the charger connected. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I700ddde291f0e4be6e3787e2da13f6d3ece736b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-21mb/starlabs/lite/glk: Correct indendation in devicetreeSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I780e2765059ad7473fe5f33c50dd0d8a561151fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/64390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-06mb/starlabs/lite: Change PMC from hidden to onStephen Edworthy
With the PMC set to hidden, on certain Operating Systems, including ZorinOS 16 and Manjaro 21.2.5, it would get stuck at a black screen when exiting from S3. With the PMC set to on, this issue no longer occurs. Signed-off-by: Stephen Edworthy <stephen@starlabs.systems> Change-Id: I0cf1be7f6919d974614f2196a0eb611cc40abe3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-04-21tpm: Refactor TPM Kconfig dimensionsJes B. Klinke
Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-04mb/starlabs/lite: Add Lite Mk IV variantSean Rhodes
Tested using upstream edk2: * Windows 10 * Ubuntu 20.04 * MX Linux 19.4 * Manjaro 21 No known issues. https://starlabs.systems/pages/starlite-specification Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id1cf2846a139004e9bec7bb27e9afe07b7e6f64f Reviewed-on: https://review.coreboot.org/c/coreboot/+/62706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-30mb/starlabs/lite: Move Verb Table to variant directorySean Rhodes
Move the verb table to variant directory to allow for different tables for different variants. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4260188057d1c3b4e6ea7c82f085fad0cc244881 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-30ec/starlabs/merlin: Make EC function names genericSean Rhodes
Rather than using `ite_`, use `ec_` so the same functions can be called for different ECs. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie61af233f731eb47772af1c82c6abdc515bc89cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/62700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-29src/mainboard/starlabs: Remove unused <option.h>Elyes Haouas
Found using: diff <(git grep -l '#include <option.h>' -- src/) <(git grep -l 'sanitize_cmos(\|get_uint_option(\|set_uint_option(\|get_uint_option(\|set_uint_option' -- src/) |grep "<" Change-Id: Ib79dfa73b8a30ae1b1e432318bd42e4e3d845af3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-03-01mb/starlabs/lite: Add StarLite Mk IIISean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iddbf2022d03735d6a0e6d098c21643f5fdc875f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 10:07:16 +0000