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2023-07-06mb/siemens/mc_ehl4: Make DRAM population depending on GPIO GPP_B5Mario Scheithauer
GPIO GPP_B5 is used as input on this mainboard. For a full-populated DRAM configuration, the input signal is connected to ground and for a half-populated configuration it is connected to 3.3 V. BUG=none TEST=Use different HW configurations and check coreboot log GPP_B5 = 0: [DEBUG] 2 DIMMs found GPP_B5 = 1: [INFO ] meminit_channels: DRAM half-populated [DEBUG] 1 DIMMs found Change-Id: I48b4a3bea7f1ff804b78b7c648a7ea1925627b8a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76245 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-06mb/siemens/mc_ehl: Make DRAM population configurableMario Scheithauer
There can be mainboard variants, which are only equipped with half-populated DRAM. For this reason, the meminit parameter for populatation should be adjustable. The default setting remains at full-populated DRAM. At mainboard variant level a different selection via individual input paths can be made. Change-Id: I390bbfa680b5505bb2230fa0740720bd9dd1fafb Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76244 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03mb/siemens/mc_ehl3/devicetree.cb: Disable USB 3.0 port 0Jan Samek
It's been decided not to use any of the USB 3.0 ports on this board. This patch disables the remaining USB 3.0 port 0, after the port 1 has already been disabled in commit d0627c7595fe ("mb/siemens/mc_ehl3/devicetree.cb: Disable USB 3.0 port 1"). BUG=none TEST=None of the USB 3.0 ports functional anymore after boot, the USB 2.0 ports continue working. Change-Id: I28465f1c5e6d3167c649da898ec60d8bb97093e2 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75836 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03mb/siemens/mc_apl1: Fix wrong register maskingMario Scheithauer
With the previous instruction the complete register was set to '0'. Correctly, only the bits 23:16 must be masked. Change-Id: Idd6e70dcb42c69cf3bc5d36db993e6def52eba58 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76177 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-07-03mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0Mario Scheithauer
Because of an incorrect transmit voltage swing, the signal must be adjusted. The factor of slices for full swing level can be corrected via the High Speed I/O Transmit Control Register 3. The appropriate value of 0.7 V was determined by using an oscilloscope. Change-Id: I965960004ca44f1b37b16ce6484000fa7fd8ad90 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-07-03mb/siemens/mc_apl1: Rename macro 'TX_DWORD3' to 'TX_DWORD3_P1'Mario Scheithauer
The offset '0xa8c' for the High Speed I/O Transmit Control Register 3 refers to SATA port 1 only. To make this clear, change the name of the define from 'TX_DWORD3' to 'TX_DWORD3_P1'. Change-Id: I09d17eeffbe84939297e739586f6b74ed3e2258b Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76174 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-07-03mb/siemens/{mc_apl3,mc_apl5,mc_apl6}: Remove TX_DWORD3 macroMario Scheithauer
A correction of Tx signal from SATA interface is not necessary on these boards currently. Therefore remove the define and the corresponding code on mc_apl5. Change-Id: I5092ee128cb35e126069d18bb3cbd635e01bbcdb Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-19soc/intel/apollolake: Switch to snake case for DisableSataSalpSupportMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'DisableSataSalpSupport'. Change-Id: I4a68ffd2b68c92434da681b5e5567329c8784c72 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75858 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-15mb/siemens/mc_ehl3/devicetree.cb: Disable USB 3.0 port 1Jan Samek
It's been decided not to use the USB 3.0 port 1 on this board anymore, so disable it also with the corresponding USB 2.0 lane. BUG=none TEST=USB 3.0 port 1 not functional anymore after boot, while others continue working. Change-Id: I2799e3d9d7232743c9480dd9611d94ed3249f53b Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-02soc/intel/apollolake: Switch to snake case for SataPortsEnableMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'SataPortsEnable'. Change-Id: I0df35125360eb42a03d5445011d72842cb2b8d7e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75553 Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-06-01mb/siemens/{mc_apl2,mc_apl5,mc_apl6}: Use SSD type for SATA portsMario Scheithauer
There are only SSD connected to SATA ports on this mainboard. To prevent misbehavior, set the correct hard drive type for enabled SATA ports. BUG=none TEST=Boot into OS and check the stability of the SSD Change-Id: I2c2b0548865e87859a1d742295e09a731bfb3f76 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-06-01mb/siemens/{mc_apl2,mc_apl5,mc_apl6}: Limit SATA speed to Gen 2Mario Scheithauer
Due to mainboard restrictions a SATA link at Gen 3 can cause issues as the margin is not big enough. Limit SATA speed to Gen 2 to achieve a more robust SATA connection. Change-Id: Ifdea4542836b9c75b5507324fbb06b9566a6fe1d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75365 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-24mb/siemens/mc_ehl1: Enable pi608gp I2C driverJan Samek
Add devicetree and Kconfig entries to enable additional configuration of the Pericom PI7C9X2G608GP PCIe switch on this board variant. The amplitude is being adjusted to 425 mV and de-emphasis level to 6.0 mV. BUG=none TEST=Read out the PCIe config space values of the switch and check if they match with the ones configured over SMBus. Change-Id: I11459f0794278ad614aa6e16c56df1ad578fe2f8 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-05-24mb/siemens/mc_ehl4: Double payload size to 256 bytes for PCIe RP #2, #3Mario Scheithauer
To improve the rate of data transfer for PCIe root port #2 (00:1c.1) and root port #3 (00:1c.2) set the max payload size to 256 bytes for both root ports. Change-Id: I553f6cf090d799fbbaafb925646c6566d6951a86 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75127 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-05-12mb/siemens/mc_ehl5: Add PTN3460 eDP-to-LVDS bridgeMario Scheithauer
This mainboard contains in addition to its base variant, mc_ehl2, an LCD panel driven through the PTN3460 eDP-to-LVDS bridge. This patch enables the PTN3460 support by adding the device to devicetree.cb and board-specific configuration parameters in lcd_panel.c. BUG=none TEST=Boot with the LCD panel attached and observe whether the picture is stable and free of artifacts coming from wrong resolution and timing. Change-Id: I196d7ceeb7ac241c9b95db2ef791a5f3ff7890a7 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-05-12mb/siemens/mc_ehl5: Add new board variant based on mc_ehl2Mario Scheithauer
This mainboard is based on mc_ehl2. In a first step, it contains a copy of mc_ehl2 directory with minimum changes. Special adaptations for mc_ehl5 mainboard will follow in separate commits. Change-Id: Id80f8eb49dd2fed0ed1ffc479d47d8669eca84c9 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-05-11mb/siemens/mc_apl5: Set Full Reset Bit into Reset Control RegisterMario Scheithauer
With the introduction of a new Linux version a problem has appeared after a software initiated reset via CF9h register. The problem manifests itself in the fact that the Linux kernel does not start after the reboot. The problem is solved by setting bit 3 to 1 in Reset Control Register (I/O port CF9h). This leads to the fact that the PCH will drive SLP_S3 active low in the reset sequence. It leads to the same behavior as in commit 04ea73ee78bc ("siemens/mc_apl3: Set Full Reset Bit into Reset Control Register") explained. Change-Id: Ia8b7f997ca6234add569da751e1070144790e258 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-05-11mb/siemens/mc_apl: Correct multi-line comment style for all Siemens APL BoardsMario Scheithauer
Change-Id: I6578aee52e6900b25441dc119383856acc480231 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-05-11mb/siemens/mc_ehl: Remove '_' from mainboard model option in Kconfig.nameMario Scheithauer
An underscore has crept into the mainboard model option for mc_ehl3 and mc_ehl4 by mistake. This patch fixes the incorrect entry. Change-Id: Ie59619877fb6341a5bbfe91c13e7692943480ad0 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75040 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-11mb/siemens/mc_ehl1: Use SSD type for SATA portsMario Scheithauer
There are only SSD connected to SATA ports on this mainboard. To prevent misbehavior, set the correct hard drive type for enabled SATA ports. BUG=none TEST=Boot into OS and check the stability of the SSD Change-Id: I116b1e36f0582956604c3c2508961ffb3de0898a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74947 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-05-04mb/siemens/mc_ehl: Remove subdir 'spd' from MakefileMario Scheithauer
Since commit 833bb448c521 ("mb/siemens/mc_ehl: Remove spd.bin from CBFS"), the subdir 'spd' is no longer necessary. Change-Id: Ibaf44e3181b2167aa83cffcc59835196e4cb5cdb Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-05-01mb/siemens/mc_ehl: Remove wrong comment regarding spd.binWerner Zeh
The support for a spd.bin from CBFS was removed for all mc_ehl boards in commit 833bb448c5213 (mb/siemens/mc_ehl: Remove spd.bin from CBFS). There is still a remaining comment in romstage_fsp_params.c referring to the removed capability. This fix removes the spd.bin related part of the comment to stay consistent with the code. Change-Id: I669ee1c33d1d1c47764640982f71129195e63f14 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74801 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-04-26mb/siemens/mc_ehl4: Enable SD cardMario Scheithauer
This mainboard has SD slot available and therefore it should be enabled. Use the same SD card configuration as for mc_ehl2 mainboard. Change-Id: Icd9b25301311679cf93b05ba83a24e551261a020 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-04-26mb/siemens/mc_ehl4: Switch RTC type and connectionMario Scheithauer
This mainboard has the RTC RV-3028-C7 connected to the I2C1. TEST: - Console Log shows no errors for RV-3028-C7 during I2C1 init - Finalize device for I2C 00:52 shows correct date and time Change-Id: I1b4115d7844a0c218fdf92cb1af2da5a95eb4337 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74652 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-26mb/siemens/mc_ehl4: Adjust USB settingsMario Scheithauer
Correct the USB settings, suitable for this mainboard. Change-Id: I943eb891e2f2d967acfd441c085063dbad49e993 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74651 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-26mb/siemens/mc_ehl4: Change NC FPGA PCIe RP connection for POST codesMario Scheithauer
Since mc_ehl4 was only a copy of mc_ehl1 in a first step, the default value of the Kconfig switch EARLY_PCI_BRIDGE_FUNCTION must be set to '0'. On this mainboard NC FPGA is connected to PCIe root port #1 (00:1c.0). Change-Id: I15035523d8575d486c3f2d0ffe3916712ee89d7d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-04-26mb/siemens/mc_ehl4: Adjust GPIOsMario Scheithauer
Since mc_ehl4 was only a copy of mc_ehl1 in a first step, the GPIOs must be adjust according to the circuit diagram for this mainboard. Change-Id: I66bfbb380e9a05b3a2c08d5d1980e9749b46ee43 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-04-11mb/siemens/mc_ehl2: Fix GPIO settings for latest HW revisionMario Scheithauer
With the latest hardware revision, the two GPIOs GPD11 and GPP_C8 are no longer used. BUG=none TEST=Checked output verbose GPIO debug messages Change-Id: Ia06f93aee4eccb0e4230f0c3ef53922d42701f21 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74201 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-03-23soc/intel/elkhartlake: Define DIMM_SPD_SIZE in SoC KconfigMichał Żygowski
The default SPD size is set to 256 bytes, instead of 512 for LPDDR4/DDR4 if not overridden by the mainboard Kconfig. This caused the SMBus libraries to read only the lower half of the DIMM SPD on protectli/vault_ehl. The lower half of the SPD passed to FSP causes a bug in DIMM change detection, which relies on the CRC of the manufacturer bytes in the upper half of the SPD (CRC of zero bytes always gives zero so no change was assumed). Setting the DIMM SPD size to 512 fixes it. Setting the SPD size in SoC will also avoid such problems in the future Elkhart Lake ports. Elkhart Lake supports only LPDDR4/DDR4 so providing the correct default of 512 bytes is an obvious thing to do. TEST=Boot Protectli VP2420 (vault_ehl) with different DIMMs and see FSP is retraining the memory instead of doing the fastboot with old DIMM data. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I998ed8781951034419cadc26c04ff1e0a124b267 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73933 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-21mb/siemens/mc_ehl4: Limit PCIe root port #4 and #5 speed to Gen 1Mario Scheithauer
Due to a non-optimal RX signal (receive) on PCIe root port #4 (00:1c.3) and #5 (00:1c.4), the speed must be limit to Gen 1. BUG=none TEST=RX signal measured with oscilloscope Change-Id: I695c0ef961290676fe421b6efd631d6e94d6d556 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73767 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-03-21mb/siemens/mc_ehl4: Enable PCIe devicesMario Scheithauer
Correct the remaining PCI devices, differing from the ehl1 mainboard. Change-Id: Ie09188b72a62c4d5cba2fcda6f60f3bc0098633e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-03-03drv/i2c/ptn3460: Add 'mainboard' prefix to mainboard-level callbacksJan Samek
As discused earlier, the callback name 'mb_adjust_cfg' was considered too generic. The new naming is chosen to be consistent with other drivers' callback names designed to be used at mainboard level. Also other functions, namely 'mb_get_edid' and 'mb_select_edid_table' are renamed accordingly. BUG=none TEST=Builds for siemens/mc_apl{1,4,5,7} and siemens/mc_ehl boards complete successfully. Change-Id: I4cbec0e72e5f03e94df0faa36765d1a6cd873a7a Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-03-02mb/siemens/mc_ehl*: Correct comment in gpio.cMario Scheithauer
There were two wrong comments in all mc_ehl gpio.c files. This patch corrects the incorrect comments. Change-Id: Iea356db177227d89b91be32a4e2367c612b77350 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72458 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-02mb/siemens/mc_ehl4: Remove TPM from devicetree and KconfigMario Scheithauer
This mainboard does not use security features like TPM. Change-Id: Ieebbf12fc844573ffadb089da78062dd2033517a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-03-02mb/siemens/mc_ehl: Move TPM Kconfig switches to variantsMario Scheithauer
The upcoming mc_ehl4 variant is the first Siemens Elkhart Lake mainboard without a TPM. For this reason, the corresponding Kconfig switches must be moved to variant level. To prevent Jenkins build from complaining, the TPM is removed in the following patch. Change-Id: Ic73ccd1b52e57c1cf1dd7337b0e28beaadbece8e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-03-02mb/siemens/mc_ehl2: Set RGMII output impedance manuallyMario Scheithauer
Measurements have shown that the automatic calibrated values for RGMII output impedances are too low. For this reason, set the PMOS value to 16 and the NMOS to 13. Change-Id: Ic3382889d3281faccb03819f9680a9763703b2a1 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73019 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-02mb/siemens/mc_ehl4: Add new board variant based on mc_ehl1Mario Scheithauer
This mainboard is based on mc_ehl1. In a first step, it contains a copy of mc_ehl1 directory with minimum changes. Special adaptations for mc_ehl4 mainboard will follow in separate commits. Change-Id: I3c1f2cf4a3dcae58895f6d14a7fce46b2825e6ba Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72427 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-02mb/siemens/mc_ehl2: Fix GPIO settingsMario Scheithauer
With the latest hardware revision, the two GPIOs GPP_B15 and GPP_E19 are no longer connected to a native function. BUG=none TEST=Checked output verbose GPIO debug messages Change-Id: I266612f041b749aa83b366497b4211fc075c7bd7 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-03-01mb/siemens/mc_ehl3/lcd_panel.c: Set LVDS re-power delay to 1 sJan Samek
The currently used panel type could work with 500 ms but increasing the value to 1 second allows to use a wider range of LVDS LCD panels, as many of them specify the delay of 1 s as minimum. BUG=none TEST=Test link stability using a panel with minimum re-power delay of 1 s. Change-Id: I2dd86e791c1212b67a80d7e6cfc474ad91b26c6b Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-02-03soc/intel/apl: Move cpu cluster to chipset.cbArthur Heymans
Change-Id: I7eaf625e5acfcefdae7c81e186de36b42c06ee67 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-02-02drv/i2c/ptn3460: Use PTN_EDID_LEN instead of constantJan Samek
Contents of the EDID are passed by a reference to an array of length 0x80, for which the macro 'PTN_EDID_LEN' has already been around. This patch makes use of this macro within the driver and mainboard implementation utilizing it. BUG=none TEST=A successful build of mc_apl{1,4,5,7} and mc_ehl3 mainboards. Change-Id: If7d254aaf45d717133bb426bd08f8f9fe5c05962 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2023-01-30src/mainboard: Remove unnecessary space after castsElyes Haouas
Change-Id: Id8e1a52279e6a606441eefe30e24bcd44e006aad Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69815 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-01-30mb/siemens/mc_ehl3/gpio.c: Disable PSE GBE0 GPIOJan Samek
Since the PSE GBE0 MAC has been disabled on this board in commit 343644006f89 ("mb/siemens/mc_ehl3/devicetree.cb: Remove TSN GbE 0"), therefore disable the corresponding GPIOs as well. BUG=none TEST=Test link detection and IP assignment on the remaining ports (PSE GBE1 and PCH GBE0) of mc_ehl3. Change-Id: Ifa055f58894688471d68b9b93fcb994fdcb2a568 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72449 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-30mb/*: Remove lapic from devicetreeArthur Heymans
The parallel mp code picks up lapics at runtime, so remove it from all devicetrees that use this codebase. Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-27drivers/i2c/ptn3460: Use cb_err in mb_adjust_cfgJan Samek
Return generic coreboot error codes from the mb_adjust_cfg callback used in mainboards instead of '-1' constant and a driver-specific success-indicating define. BUG=none TEST=Boards siemens/mc_apl{1,4,5,7} and siemens/mc_ehl3 build correctly. Change-Id: I5e0d4e67703db518ed239a845f43047f569b94ec Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-27mb/siemens/mc_apl1/var/mc_apl5: Enable early POSTJan Samek
Enable early POST code display on this variant using the common mc_apl1 baseboard functionality. BUG=none TEST=Boot on mc_apl5 and observe that POST codes are displayed before DRAM training. Change-Id: I390e0ab09ca830637e7a991db77e994d6c358e75 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72386 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22mb/siemens/mc_apl1/var/mc_apl6: Enable early POSTJan Samek
Enable early POST code display on this variant using the common mc_apl1 baseboard functionality. BUG=none TEST=Boot on mc_apl6 and observe that POST codes are displayed before DRAM training. Change-Id: I2a52c241c383f8ebcf05052e9bc0ba13e63e3728 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-22mb/siemens/mc_apl1: Move POST logic to mainboard levelJan Samek
Move logic previously used only in the mc_apl2 variant to the mainboard level so that other variants can also make use of it without code duplication. This functionality on the mc_apl6 variant will be enabled in a follow-up patch. BUG=none TEST=Boot on siemens/mc_apl2 and observe that the POST codes are displayed before DRAM training. Change-Id: I762e328ad06c047d911ce1fc40f12a66cbd14e11 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-20mb/siemens: Unify and clean lcd_panel.c coding styleJan Samek
With the addition of the mc_ehl3 board variant, a few points about commenting the code arose either from the review or during the implementation itself. This patch unifies structure of these files, which have a similar structure across more Siemens boards utilizing the PTN3460 eDP-to-LVDS bridge. BUG=none TEST=Check that images for the affected boards can be built. Change-Id: I59820362e1f87e296c5548b9c3cecba4d2710fe7 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72068 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20mb/siemens/mc_ehl3: Add PTN3460 eDP-to-LVDS bridgeJan Samek
This board contains in addition to its base variant, mc_ehl2, an LCD panel driven through the PTN3460 eDP-to-LVDS bridge. This patch enables the PTN3460 support by adding the device to devicetree.cb and board-specific configuration parameters in lcd_panel.c, based upon a similar implementation in siemens/mc_apl7. BUG=none TEST=Boot with the LCD panel attached and observe whether the picture is stable and free of artifacts coming from wrong resolution, timing etc. Change-Id: Ib8a1a6f47053406e42554c2dd33684165d54be08 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-19mb/siemens/mc_ehl3: Use device/mmio.h instead of device/pci_ops.hJan Samek
The {read,write}{16,32}() functions used in this file come from the mmio.h header, so include it directly. BUG=none TEST=Read out the SD card controller (device 1a.1) PCI registers in Linux and check whether the values reflect the ones defined in this file. Change-Id: Iff7b55ef2bf98371b7d7d9114ccf3ebed64772a2 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72009 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-18mb/siemens/mc_ehl: Remove '_' from mc_ehl3 part numberJan Samek
Change MAINBOARD_PART_NUMBER Kconfig value for mc_ehl3 from "MC_EHL3" to "MC EHL3". Change-Id: Ie548607c5fb62faaed4921af714bc9b912e558a8 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71775 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-13mainboard: Remove duplicated <soc/gpio.h>Elyes Haouas
<gpio.h> chain-include <soc/gpio.h>. Change-Id: Ia57d5cd33c70b6a755babd4db56c64c0e3666f9f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-11mb/siemens/mc_ehl1: Enable real-time tuningWerner Zeh
Enable the real-time tuning to improve performance in the real-time environment for this mainboard. Change-Id: I91ad7ca58add92b5cc66148aff8378890ee217eb Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71234 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-10mb/siemens/mc_ehl1: Limit SATA speed to Gen 2Werner Zeh
Due to mainboard restrictions a SATA link at Gen 3 (6 Gbps) can cause issues as the margin is not big enough. Limit SATA speed to Gen 2 to achieve a more robust SATA connection. Change-Id: Ia79998db5f959528a4e8e29e570a7f55283adee1 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71230 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-23mb/siemens/mc_apl{4,7}: Limit I2C bus speed to 100 kHz on bus 7Werner Zeh
Due to a high I2C bus load on the mainboard I2C frequency of 400 kHz leads to poor signaling. Therefore limit the I2C speed to 100 kHz for this bus. In addition, add a generic I2C device with 100 kHz bus speed to the devicetree so that the OS will not switch to higher clock rates, too. Test= Measure the I2C signals at coreboot and OS runtime and ensure the clock is always at 100 kHz. Change-Id: I6b0a642cd3f5b77331663ac8c76ed0a116ae77ca Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71227 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21mb/siemens/mc_ehl3/devicetree.cb: Remove TSN GbE 0Jan Samek
Remove the PSE TSN GbE device #0 as it's unused on the board and not visible during the PCI enumeration. Change-Id: I4a7d0e437c4f4a12d3a07564cddeafb7c697c6d3 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70700 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21mb/siemens/mc_ehl3/mainboard.c: Remove XIO2001 register tweaksJan Samek
Contrary to mc_ehl2, which this variant is based on, this board doesn't contain the TI XIO2001 PCIe-to-PCI bridge, which makes the attempts to modify the bridge's registers unnecessary. Change-Id: I6597ceb78e4c790c08a0dfa9535dece33a8f95b8 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70854 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17mb/siemens/mc_ehl3/devicetree.cb: Adapt PCIe root port settingsJan Samek
Based upon hardware differences from mc_ehl2, disable RP7 and enable RP3 and RP5. Change-Id: Iecaa3098c3e4c9ce15254bb8bd1fe6da86d6e706 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70689 Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17mb/siemens/mc_ehl3: Add board variant based on mc_ehl2Jan Samek
Add a new mc_ehl variant, which is based on mc_ehl2 implementation. This patch uses a copy of mc_ehl2 with changes only in naming as a starting point for the new mc_ehl3 variant. Follow-up patches will introduce the functional changes against mc_ehl3. Change-Id: Ie8c18b4f16d88b175ce576c2ef4c2e6ee0b4c306 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-12-10treewide: Include <device/mmio.h> instead of <arch/mmio.h>Elyes Haouas
<device/mmio.h>` chain-include `<arch/mmio.h>: https://doc.coreboot.org/contributing/coding_style.html#headers-and-includes Also sort includes while on it. Change-Id: Ie62e4295ce735a6ca74fbe2499b41aab2e76d506 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-09mb/siemens/*/Makefile.inc: Remove path to non-existent folderElyes Haouas
Found using 'Wmissing-include-dirs' command option. Change-Id: Ie9ff43432215ebc89e6c1ea5f86b248e7fecd943 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70396 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-01mb/siemens/mc_ehl2: Disable GSPI2 controllerMario Scheithauer
GSPI2 interface is not used on this mainboard and can be disabled. It will in addition remove the warning of a leftover static device in the log. Change-Id: I6e7462312953d50385ca7bb2f2e0abb8fc3a5886 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-11-25mb/siemens/mc_ehl2: Disable L1 prefetcherMario Scheithauer
As for mainboard mc_ehl1, a hard real-time dependency is also required for this mainboard. The L1 prefetcher on Elkhart Lake is too aggressive which in the end leads to an increased number of cache misses. Disabling the L1 prefetcher boosts up the performance (in some cases by more than 10 %) in this specific use case. Change-Id: I07b27dd672533e693a6c2987d16f54333850760e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-11-24mb/siemens/mc_ehl2: Enable downshift for Marvell PHYsMario Scheithauer
Set downshift counter to 2 for all Marvell PHYs on this mainboard before the PHY downshifts to the next highest speed. Change-Id: I32b5f25a3e1e0f962dff3110143e236992ef8e7d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69887 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24mb/siemens/mc_ehl2: Enable Marvell PHY interruptMario Scheithauer
On this mainboard Marvell PHY INTn is routed to LED[2] pin. Change-Id: I28a78afdcf0599bb998f906ce8056a0586e24f33 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69434 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24mb/siemens/mc_ehl2: Enable Marvell PHY 88E1512 driverMario Scheithauer
This mainboard has three Marvel PHYs connected to the internal SOC GbE controllers. The default LED status after HW reset of this PHYs shows a different mode than what is needed. LED[2] is not connected on this mainboard. This patch sets the following LED status: LED[0] - 7 = On - 1000 Mbps Link, Off - Else LED[1] - 1 = On - Link, Blink - Activity, Off - No Link LED[2] - not connected TEST=Try different register values to verify LED feature. Change-Id: I51d817bc720bf787279777f503efdc17dbb1274d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69387 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-18mb/siemens/mc_ehl2/devicetree.cb: Use RV3028 bus_speed instead of dummy i2c ↵Jan Samek
device Instead of creating a dummy I2C device in order to force Linux to decrease the I2C bus speed, use the own 'bus_speed' field of RV3028 device config structure. Linux should always set the bus speed to the speed of the slowest device sitting on the bus. Hence the dummy device is not needed here anymore. BUG=none TEST=See if the RV3028 RTC is visible and working (date/time can be set/read) in Linux. At the time, a driver modification is needed to add a match table for the "MCRY3028" ACPI HID. A proper kernel patch is pending. Change-Id: I6e269dc67d1fe2a6747fcf3bee224def7b553f08 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69544 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-11-09mb/siemens/mc_ehl2: Provide I2C timing parameter for SSDTWerner Zeh
Provide timing parameter for SSDT generation to achieve the requested 100 kHz speed with a high accuracy. Test: Measure I2C bus clock, high and low times during I2C access from Linux and confirm they match the specification. Change-Id: Ifb6019421b612133b8f25c076519bc0e7200dad8 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-09mb/siemens/mc_ehl2: Add dummy I2C devices to limit the I2C speed in OSWerner Zeh
In Linux, the I2C speed defaults to 400 kHz if there is no device registered in ACPI which requests a different speed. Due to board limitations (layout, bus load), 400 kHz are too fast which results in a timing violation. Therefore, add a dummy I2C device to both used I2C buses (I2C1 and I2C2) with a speed of 100 kHz. This will limit the bus speed in Linux accordingly. Change-Id: I507c53c9ec7f763cef18903609231b1a66ed98fa Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-10-29mb/siemens/mc_ehl: Remove spd.bin from CBFSWerner Zeh
The SPD data for DRAM init has moved into the hwinfo data structure and is therefore not used from spd.bin anymore. spd.bin will not receive any updates, changes will only be done in hwinfo. There is no reason to keep spd.bin around so remove it for both variants. Change-Id: Ie6091b655ba7ff2e01b684266ce34b85593b8623 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-27mb/siemens/mc_apl2: Enable early POST through NC_FPGAJan Samek
Enable early POST code output for this mainboard, using the NC FPGA device on PCIe. This requires the parent PCI bridge to be initialized early. BUG=none TEST=boot on siemens/mc_apl2 and observe whether the POST codes coming from before FSP-M init are visible Change-Id: Ice5fe26e11d0513e6bb0a20f1d8f0483d7b3dc6a Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-10-25mb/siemens/mc_ehl1: Disable L1 prefetcherWerner Zeh
The highly real time driven application executed on mc_ehl1 has shown that the L1 prefetcher on Elkhart Lake is too aggressive which in the end leads to an increased number of cache misses. Disabling the L1 prefetcher boosts up the performance (in some cases by more than 10 %) in this specific use case. Change-Id: Id09a7f8f812707cd05bd5e3b530e5c3ad8067b16 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68668 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-10-22mb/siemens/mc_ehl: Add FIVR config to devicetree for all variantsWerner Zeh
Add a config for FIVR in devicetree for both, mc_ehl1 and mc_ehl2 variants in order to provide the real delay value for the VCC supply rail. This delay is needed to enable proper switching between different VCC levels based on current system state. Change-Id: Ibccb8ea1b42ccd2ff0a37cbd9651528a2a55ebd6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22mb/siemens/mc_apl*: Enable early PCI bridge before FSP-MAngel Pons
Apollo Lake seems to start with PCIe root ports unusable/uninitialized before FspMemoryInit() is called and FSP-M properly initializes these root ports. However, we need the root ports accessible before FspMemoryInit() in certain cases, such as emitting POST codes through a PCIe device. For the initialization to happen properly, certain register writes specified in Apollo Lake IAFW BIOS spec, vol. 2 (#559811), chapter 3.3.1 have to be done. BUG=none TEST=Boot on siemens/mc_apl2 with NC_FPGA_POST_CODE enabled and check that the POST codes are emitted before FspMemoryInit(). Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68223 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-07mb/siemens/mc_ehl2: Use preset driver strength for SD-CardMario Scheithauer
The intention of predefining driver strength is to avoid that the OS SD-Card driver changes this setting. Change-Id: I02fdac94462da1cd77f8dc972faf16f28d94c946 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-09-22mb/siemens/mc_apl7: Enable libgfxinit for the boardJan Samek
Add the gma-mainboard.ads for display output definition and enable the libgfxinit usage in mainboard Kconfig. Change-Id: I7e7a44736a8136b5320821e744134c7d64c7f1b4 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67683 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-22mb/siemens/mc_apl7/Kconfig: Enable PTN3460 early initJan Samek
Enable early initialization of the PTN3460 DP-to-LVDS bridge on this board in order to allow showing the bootsplash screen at coreboot runtime. Change-Id: Ib1b727cef5fb8bea2d6d6c9896ad0107caeea51a Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67682 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19mb/siemens/mc_apl1: Do not wait for legacy devices on mc_apl7Werner Zeh
Since there are no legacy devices on the variant mc_apl7 do not wait for them on mc_apl7. Change-Id: Ia4e6c0fb495a347be51bd6604a1d9b73098fb7b6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67684 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-07mb/siemens/mc_ehl2: Limit SD-Card speed modes to DDR50Werner Zeh
Due to layout restrictions on mc_ehl2, the SD-card interface is limited to operate in DDR50 mode. The alternative modes SDR104 and SDR50 are not supported. Limit the capabilities in the SD card controller to DDR50 mode only so that the SD card driver in OS will choose the right mode for operation even if the attached SD card supports higher modes. Change-Id: Idc7f1466ec71f4218f6b957cadeeffadd069eb2d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-09-07mb/siemens/mc_ehl2: Set I2C bus 1 speed to 100 kHzWerner Zeh
Since the new RTC is located in I2C bus 1 now, set the bus speed to 100 kHz as well. Change-Id: Ica9468e559bc654545592a9b4d23f3164eafca8a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67102 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-07mb/siemens/mc_ehl2: Change to new RTC RV3028-C7Werner Zeh
Since the latest redesign a new RTC was introduced on mc_ehl2. Instead of the old RX6110SA the new Micro Crystal RTC RV3028 is used now. Since the address of this new RTC conflicts with an EEPROM on I2C bus 2, the new RTC was moved to I2C bus 1. As the mainboard is not finished yet, there are no incompatibility issues with this change. Every new mainboard will have the new RTC and the older mainboards are not delivered yet. Change-Id: I3dd00855b8c9b22bdea21d3c8563cdb392868751 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-09-07mb/siemens/mc_ehl: Move RTC Kconfig option to variant levelWerner Zeh
With a redesign of mc_ehl2 the used RTC was changed. In order to be able to select a different RTC type for every variant move the RTC Kconfig switch into the variant's Kconfig file. Change-Id: Ia24703ede6a935e3b9886df87237857baec7d6a0 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67100 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-16mb/**/dsdt.asl: Drop misleading "OEM revision" commentAngel Pons
It is highly unlikely that the "OEM revision" of the DSDT is 0x20110725 on mainboards with a chipset not yet released on 2011-07-25. Since this comment is most likely to have been copy-pasted from other boards, drop it from boards which use a chipset newer than Sandy/Ivy Bridge. Change-Id: If2f61d09082806b461878a76b286204ae56bf0eb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-08-16mb/**/dsdt.asl: Drop superfluous commentsAngel Pons
These comments don't add much value, so remove them. Change-Id: I7e9692e3fe82345cb7ddcb11c32841c69768cd36 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66713 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-06-27mb/siemens/mc_apl7: Disable VBOOT and TPMUwe Poeche
mc_apl7 does not use security features like VBOOT and TPM. Test: flash mc_apl4 mainboard and ensure the disabled features via log. Change-Id: I16683b92deb047208848b69c5aa79dc4212ce930 Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65284 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-06-23mb/siemens/mc_apl1: Add new mainboard variant mc_apl7Uwe Poeche
This patch adds a new mainboard variant called mc_apl7 which is based on mc_apl4. So far only the names have been adjusted with no further changes. Following commits will introduce the needed changes for this mainboard variant. Test: build mc_apl7, flash to mc_apl4 and compare log level 8 output Change-Id: Ie9f2f5c29d071de442f8f3e3eaf4b3c2a6b8920f Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65283 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-20soc/intel/apollolake: Hook Up SataPortEnable to devicetreeSean Rhodes
Hook Up SataPortsEnable to the devicetree. As the default value is 0, set both [0] and [1] in all mainboards so they aren't affected. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ica8cf9484a6e6fe4362eabb8a9a59fcaf97c1bd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64524 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-26soc/intel/cannonlake: Hook up FSP hyper-threading setting to option APIFelix Singer
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting from the FSP to the option API so that related mainboards don't have to do that. Unless otherwise configured (e.g. the CMOS setting or overriden by the mainboard code), the value from the Kconfig setting `FSP_HYPERTHREADING` is used. Also, remove related code from the following mainboards, since it is obsolete now. * siemens/chili * starlabs/laptop/cml Change-Id: I173b87da5ce76549672c50ba30204cd77be8b82f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-05-23mb/siemens/mc_ehl: Disable RAPLUwe Poeche
Disable RAPL for all mainboards based on mc_ehl for stable real time mode of CPUs. Test: Boot mc_ehl1 with this patch and ensure the bits in the MCBAR register are cleared. Change-Id: Ie58a4b6444d5be088ac2b25ff0a2f5cd33120ace Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-21mb/siemens/mc_ehl2: Invert PHY IRQ from falling edge to rising edgeMario Scheithauer
There are three external Marvell PHY 88E1512 on this mainboard. The PHY IRQ comes with a falling edge but the EHL MAC side needs a rising edge signal. For that reason, we need an inversion of the IRQ polarity. Change-Id: Id3caf582b4434b046779f5733e6ad9b57528ce35 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-20mb/siemens/mc_ehl2: Quick fix for PSE TSN phy interface typeLean Sheng Tan
Based on quick fix on this commit 7b0fe59be (soc/intel/ehl: Fix logical bug for PseTsnGbePhyInterfaceType), disable PSE TSN SGMII as the original intention is to set the PSE TSN phy interface as RGMII. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Id2e05b19f156621a945110791038bc0d19a0aad0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-05-18intel/common/block: Provide RAPL and min clock ratio switches in commonUwe Poeche
There are two APL specific config switches for RAPL and min. cpu clock (APL_SKIP_SET_POWER_LIMITS, APL_SET_MIN_CLOCK_RATIO). These switches could be used in future in other CPU platforms. Move them to common code instead of having them just for one SOC. Test: Make sure that the clock ratio (MSR 0x198) and the RAPL settings (MSR0x610) do not change with this patch applied on mc_apl{1,4,5} mainboard. Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-17mainboard/**/devicetree.cb: Fix typoAngel Pons
repalcement ---> replacement Change-Id: I486170e89f75fa7c01c7322bb8db783fd4f61931 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64404 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-17soc/intel/elkhartlake: Enable SMBus depending on dev stateAngel Pons
Program the `SmbusEnable` FSP UPD according to the SMBus PCI device's state in the devicetree. This avoids having to manually make sure the SMBus PCI device and the `SmbusEnable` setting are in sync. Change-Id: I275a981f914a55dc57a75e7d436912ff0255a293 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64402 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-17mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridgeMario Scheithauer
On this mainboard there are legacy PCI devices connected behind a PCIe-2-PCI bridge. Not all clock outputs of this bridge are used. This patch disables the unused PCI clock outputs on the XIO2001 bridge. Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63931 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16mb/siemens/mc_ehl2: Enable TSN GbE driverMario Scheithauer
This variant uses all three EHL Ethernet GbE-TSN Controller so enable the TSN GbE driver in order to set the needed MAC addresses. The required function to retrieve a valid MAC address was already implement in the common mainboard.c for mc_ehl. TEST: - Boot mc_ehl2 into Linux and check MAC addr via 'ip a' Change-Id: Ia052c44feb606f9e1d31d047f2acc67e3226a895 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-16mb/siemens/mc_ehl2: Set PCH TSN link speed to 1 Gbps in devicetreeMario Scheithauer
TSN runs in SGMII mode on this mainboard. This requires setting the link speed to 1 Gbps. Change-Id: I9f1da971b4de5671d6d38be6dbc50edbbe20d157 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-16mb/siemens/mc_ehl2: Adjust PSE TSN settings in devicetreeMario Scheithauer
This mainboard uses all three internal Ethernet GbE-TSN controllers. Two of them are initialized by the Programmable Services Engine (PSE). This patch enables the Serial Gigabit Media Independent Interface (SGMII) mode for GbE PSE0 and GbE PSE1. By setting PCH PSE DMA pins to host owned, the IO is under control of the IA processor cores through system software. TEST: - Boot mc_ehl2 into Linux and check inet addr via 'ip a' Change-Id: I74e660548b2c44d5dbdb6023d5a36cfdd7e96f43 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-04-21tpm: Refactor TPM Kconfig dimensionsJes B. Klinke
Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 20:33:57 +0000