index
:
coreboot.git
macbookair5_2
macbookpro10_1
main
master
mbp101_medisable
mbp101_medisable_1
mbp82
x230
my copy of coreboot
User &
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
mainboard
/
siemens
/
sitemp_g1p1
Age
Commit message (
Expand
)
Author
2012-05-04
siemens/sitemp_g1p1: Drop debug code
Patrick Georgi
2012-04-20
Refactor some alignment handling
Patrick Georgi
2012-03-08
Unify Local APIC address definitions
Patrick Georgi
2012-02-22
amd/sb600: Move HAVE_HARD_RESET to southbridge
Patrick Georgi
2012-02-17
Remove whitespace.
Patrick Georgi
2011-11-01
remove trailing whitespace
Stefan Reinauer
2011-10-28
siemens/sitemp_g1p1: Add more devices to PIR and MP table
Patrick Georgi
2011-10-13
Use default table creator macro for all SSDTs
Stefan Reinauer
2011-10-13
siemens/sitemp_g1p1: Don't mess with virtual wire settings
Patrick Georgi
2011-10-13
siemens/sitemp_g1p1: Get rid of bus_isa and bus_type
Patrick Georgi
2011-10-13
mptable: Refactor mptable generation some more
Patrick Georgi
2011-10-13
mptable: Get rid of fixup_virtual_wire
Patrick Georgi
2011-10-13
mptable: Refactor lintsrc generation
Patrick Georgi
2011-05-13
siemens/sitemp_g1p1: Adapt read_option() to latest changes
Josef Kellermann
2011-05-12
Remove uart_init() in Siemens sitemp-g1p1
Patrick Georgi
2011-05-11
Add Siemens SITEMP-G1 board
Josef Kellermann