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mc_apl1
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Author
2019-03-15
mb/mc_apl1/variants/mc_apl5: Drop unused '#include <lib.h>'
Elyes HAOUAS
2019-03-06
mb/siemens/{mc_apl1,mc_tcu3}: Fix typo on "Display"
Elyes HAOUAS
2019-03-04
device/mmio.h: Add include file for MMIO ops
Kyösti Mälkki
2019-03-04
arch/io.h: Add missing includes
Kyösti Mälkki
2019-03-01
device/pci: Fix PCI accessor headers
Kyösti Mälkki
2019-02-13
siemens/mc_apl4: Enable HW SPI TPM on mainboard mc_apl4
Uwe Poeche
2019-02-13
siemens/mc_apl2: Remove double entry from devicetree
Mario Scheithauer
2019-02-05
mb/siemens/mc_apl1: Enable VTD for mc_apl2 and mc_apl5
Werner Zeh
2019-01-30
siemens/mc_apl2: Change SERIRQ mode
Mario Scheithauer
2019-01-30
siemens/mc_apl2: Correct whitespace of devicetree
Mario Scheithauer
2019-01-30
siemens/mc_apl2: Activate TPM support
Mario Scheithauer
2019-01-16
siemens/mc_apl4: Change UART_FOR_CONSOLE index
Mario Scheithauer
2019-01-11
siemens/mc_apl1: Use INTEL_LPSS_UART_FOR_CONSOLE
Mario Scheithauer
2018-12-17
siemens/mc_apl4: Enable RTC RX6110SA on this mainboard
Uwe Poeche
2018-12-17
siemens/mc_apl4: Enable LVDS Display on mc_apl4
Uwe Poeche
2018-12-17
siemens/mc_apl4: Add GPIO configuration
Uwe Poeche
2018-11-30
cpu/intel/common: Use a common acpi/cpu.asl file
Arthur Heymans
2018-11-29
siemens/mc_apl5: Disable PCI clock outputs on XIO bridges
Mario Scheithauer
2018-11-29
siemens/mc_apl5: Set bus master bit for on-board PCI device
Mario Scheithauer
2018-11-29
siemens/mc_apl5: Enable SDCARD
Mario Scheithauer
2018-11-27
siemens/mc_apl5: Adjust the settings for the PCIe root ports
Mario Scheithauer
2018-11-26
siemens/mc_apl1/variants/mc_apl*: Remove unneeded PTN read
Mario Scheithauer
2018-11-23
siemens/mc_apl4: Set CPU clock to minimum ratio
Werner Zeh
2018-11-23
mb: Set coreboot as DSDT's manufacturer model ID
Elyes HAOUAS
2018-11-21
ACPI: Fix DSDT's revision field
Elyes HAOUAS
2018-11-18
siemens/mc_apl5: Add new mainboard variant mc_apl5
Mario Scheithauer
2018-11-16
mb/siemens/mc_apl1/variants/mc_apl*: Remove unused BOARD_SIEMENS_MC_APL*_VAR
Elyes HAOUAS
2018-11-16
src: Remove unneeded include <lib.h>
Elyes HAOUAS
2018-11-16
mb/*/*/Kconfig: Use CONFIG_VARIANT_DIR for devicetree
Peter Lemenkov
2018-11-16
siemens/mc_apl4: Clean up ramstage
Mario Scheithauer
2018-11-16
siemens/mc_apl4: Overwrite swizzle data for LPDDR4
Mario Scheithauer
2018-11-12
siemens/mc_apl4: Enable SDCARD
Mario Scheithauer
2018-11-12
siemens/mc_apl4: Remove external RTC from I2C0
Mario Scheithauer
2018-11-12
siemens/mc_apl4: Enable all PCIe root ports
Mario Scheithauer
2018-11-12
siemens/mc_apl4: Remove reduced clock rate for I2C0
Mario Scheithauer
2018-11-12
siemens/mc_apl4: Disable CLKREQ of PCIe root ports
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Disable PCI clock outputs on XIO bridges
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Set Full Reset Bit into Reset Control Register
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Set bus master bit for on-board PCI device
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Remove the correction of the Tx signal for SATA
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devices
Mario Scheithauer
2018-11-07
siemens/mc_apl4: Add new mainboard variant mc_apl4
Mario Scheithauer
2018-11-07
siemens/mc_apl2: Adjust GPIO settings for mc_apl2
Mario Scheithauer
2018-11-07
siemens/mc_apl3: Disable I2C7 over devicetree
Mario Scheithauer
2018-11-07
siemens/mc_apl3: Enable all PCIe root ports
Mario Scheithauer
2018-11-07
siemens/mc_apl3: Remove reduced clock rate for I2C0
Mario Scheithauer
2018-11-07
siemens/mc_apl3: Disable CLKREQ of PCIe root ports
Mario Scheithauer
2018-11-07
siemens/mc_apl3: Adjust GPIO settings for mc_apl3
Mario Scheithauer
2018-10-30
siemens/mc_apl3: Add new mainboard variant mc_apl3
Mario Scheithauer
2018-10-08
Move compiler.h to commonlib
Nico Huber
2018-10-06
soc/intel/common, mb/google, mb/siemens: Use lower case x for RXD
Furquan Shaikh
2018-10-04
mc_apl1: Set up SPI OPCODE menu before locking
Werner Zeh
2018-10-01
siemens/mc_apl1: Activate clock spreading for PTN3460
Mario Scheithauer
2018-09-27
siemens/mc_apl1: Add new mainboard variant mc_apl2
Mario Scheithauer
2018-09-27
siemens/mc_apl1: Make the DDR memory swizzle data configurable
Mario Scheithauer
2018-08-31
siemens/mc_apl1: Correct the Tx signal from SATA interface
Mario Scheithauer
2018-08-28
siemens/mc_apl1: Extend circuit life by clock gating and power gating
Mario Scheithauer
2018-08-27
siemens/mc_apl1: Disable PCI clock outputs on XIO bridge
Mario Scheithauer
2018-08-24
siemens/mc_apl1: Select DDR50 mode for eMMC
Mario Scheithauer
2018-08-23
siemens/mc_apl1: Make adjustments for the 1st redesign of this mainboard
Mario Scheithauer
2018-08-23
siemens/mc_apl1: Move board specific things to mc_apl1 variant
Mario Scheithauer
2018-06-06
soc/intel/common/block: Add common chip config block
Subrata Banik
2018-05-08
mb/siemens: Get rid of device_t
Elyes HAOUAS
2018-04-27
siemens/mc_apl1: Move board specific things to mc_apl1 variant
Mario Scheithauer
2018-04-26
siemens/mc_apl1: Provide baseboard and variant concepts
Mario Scheithauer
2018-04-24
compiler.h: add __weak macro
Aaron Durbin
2018-04-13
siemens/mc_apl1: Fix accuracy issue with IDT PMIC
Mario Scheithauer
2018-04-11
siemens/mc_apl1: Make DRAM configuration more flexible
Mario Scheithauer
2018-03-16
soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array
Furquan Shaikh
2017-11-07
siemens/mc_apl1: Select CONFIG_NC_FPGA_NOTIFY_CB_READY
Mario Scheithauer
2017-11-03
siemens/mc_apl1: Enable I2C0 with 100kHz
Mario Scheithauer
2017-11-03
siemens/mc_apl1: Set coreboot ready LED
Mario Scheithauer
2017-11-03
siemens/mc_apl1: Add legacy IRQ routing for PCI devices
Mario Scheithauer
2017-09-26
Use stopwatch_wait_until_expired where applicable
Jonathan Neuschäfer
2017-09-21
siemens/mc_apl1: Move SCI to IRQ 10
Mario Scheithauer
2017-09-14
siemens/mc_apl1: Add delay to wait for legacy devices
Werner Zeh
2017-09-08
siemens/mc_apl1: Disable internal UARTs
Mario Scheithauer
2017-09-08
siemens/mc_apl1: Set bus master bit for on-board PCI device
Mario Scheithauer
2017-08-18
include/device: Split i2c.h into three
Nico Huber
2017-08-15
soc/intel/common/block: Add LPC Common code and use it for APL
Ravi Sarawadi
2017-07-27
siemens/mc_apl1: Select skip RAPL configuration
Mario Scheithauer
2017-07-20
siemens/mc_apl1: Activate ECC for DRAM
Mario Scheithauer
2017-07-20
siemens/mc_apl1: Include platform.asl
Mario Scheithauer
2017-07-18
siemens/mc_apl1: Disable SDCARD
Mario Scheithauer
2017-07-13
Rename __attribute__((packed)) --> __packed
Stefan Reinauer
2017-06-30
mb/siemens/mc_apl1: Set up RTC backup mode to primary cell
Werner Zeh
2017-06-23
siemens/mc_apl1: Enable decoding for COM 3 on LPC
Mario Scheithauer
2017-06-23
siemens/mc_apl1: Disable XDCI
Mario Scheithauer
2017-06-13
siemens/mc_apl1: Enable decoding for COM 3 on LPC
Mario Scheithauer
2017-06-13
siemens/mc_apl1: Use Siemens NC FPGA driver
Mario Scheithauer
2017-05-17
siemens/mc_apl1: Program eMMC DLL settings
Mario Scheithauer
2017-05-17
siemens/mc_apl1: Select external 8250 UART
Mario Scheithauer
2017-05-11
siemens/mc_apl1: Add usage of external RTC RX6110 SA
Mario Scheithauer
2017-05-11
siemens/mc_apl1: Correct GPIO settings
Mario Scheithauer
2017-05-05
mainboard/siemens/mc_apl1: remove unnecessary header
Aaron Durbin
2017-04-04
siemens/mc_apl1: Activate PTN3460 eDP to LVDS bridge IC
Mario Scheithauer
2017-03-29
siemens/mc_apl1: Adjust gpio settings
Mario Scheithauer
2017-03-15
siemens/mc_apl1: Clean up the code
Mario Scheithauer
2017-02-20
siemens/mc_apl1: Set MAC address for all available i210 MACs
Mario Scheithauer
2017-02-15
siemens/mc_apl1: Make basic settings for booting the mainboard
Mario Scheithauer
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