| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-11-29 | siemens/mc_apl5: Disable PCI clock outputs on XIO bridges | Mario Scheithauer |
| 2018-11-29 | siemens/mc_apl5: Set bus master bit for on-board PCI device | Mario Scheithauer |
| 2018-11-29 | siemens/mc_apl5: Enable SDCARD | Mario Scheithauer |
| 2018-11-27 | siemens/mc_apl5: Adjust the settings for the PCIe root ports | Mario Scheithauer |
| 2018-11-26 | siemens/mc_apl1/variants/mc_apl*: Remove unneeded PTN read | Mario Scheithauer |
| 2018-11-18 | siemens/mc_apl5: Add new mainboard variant mc_apl5 | Mario Scheithauer |
 |
index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |