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Until now some FSP-S parameters were configured for Siemens APL
mainboards via the Binary Configuration Tool (BCT). For simplification,
the original APL FSP binary should now be used. For this purpose, the
corresponding FSP-S parameters are set via devicetree, respectively via
mainboard_silicon_init_params accordingly.
The following parameters are affected:
- Disable CPU power states (C-states)
- Set lowest Max Pkg Cstate - PkgC0C1
- Disable PCIe Hot Plug for all enabled RPs
- Disable PCIe Transmitter Half Swing for all RPs
- Disable PCIe Active State Power Management (ASPM) for all RPs
- Disable PCIe L1 Substates for all RPs
TEST:
- Compare old with new coreboot log on mc_apl5, found no differences
- Boot Linux v4.4 and check output of 'lspci'
Change-Id: I5af627defd6426140cc9a74bb18db400a8971d72
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Enable CSE PCI device Bus 0: Device 0x0f: Function 0x00 to let
Intel common cse block code can use this device.
Calling me_read_config32(offset) function from ramstage:
Without this CL :
HECI: Global Reset(Type:1) Command
BUG: me_read_config32 requests hidden 00:0f.0
PCI: dev is NULL!
With this CL :
HECI: Global Reset(Type:1) Command
HECI: Global Reset success!
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I97d221ae52b4b03ecd859d708847ad77fe4bf465
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I73695152ec8d8ab2dabf8421ef2405f70de0f4ba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42795
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch replaces and cleans up the redundant PTN3460 driver files in
/mainboard/siemens directories by using the now available driver in
src/drivers/i2c/ptn3460 and providing mainboard specific functions to
the driver.
TEST=Display is working on Siemens mainboards (e.g. mc_tcu3, mc_apl1, ...).
Change-Id: I976a502e7176a356bab772758250db3cdff529b9
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36643
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We need to reduce the eMMC bus speed for these Apollo Lake mainboards
because of a limitation on Intel side for industry use cases.
Change-Id: Ide6a1a302001c0752d149bfdab175a27c8f8cc35
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This patch enables TPM on SPI and adds the needed devicetree entry for
mc_apl5.
TEST=Build coreboot for mc_apl5 board and check the TPM console output.
In addition the TPM was correctly verified by our Linux driver.
Change-Id: Iafc967c7a2bfee9bdb9b6591d12328620e2887cc
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33173
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With commit
'4074ce0cc7 (intel/apollolake: Add HDA to disable_dev function)'
FSP is now requested to switch off HDA PCI device if it is disabled in
devicetree. Doing so results in a warm restart. Normally this event
will be stored in CMOS RAM (if the descriptor is configured to do so)
and therefore no further resets are requested by FSP on the next boots
as long as CMOS RAM is kept alive.
The Siemens mainboards based on Apollo Lake do not have a CMOS battery
and therefore the CMOS is not backed up. This leads to reset requests
from FSP after PCI enumeration on every boot. To avoid this reset enable
HDA in devicetree for these mainboards. Though we do not have any usage
of HDA it should not be an issue that the HDA device is now enabled. The
benefit is though that no reset is requested anymore by FSP.
Change-Id: I637c7c01d73350700c6066fee74fecbb5b93b221
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32295
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is no device on I2C0 which requires a lower clock rate.
Change-Id: Iaf01be5ea4839c54eb2f0ba95bca272970c24bdb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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These boards need a working VTD therefore enable this feature.
Change-Id: I74c64bf1bd66188c4c32b85c66683dafd0e1fd38
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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This mainboard also has a SD slot.
Change-Id: I969e8ecb27aee4c8be212e67dfe6bd807ecd3b2f
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This mainboard has four connected PCIe devices. The required root ports
are switched on and configured.
Change-Id: I82b13e1d245a172762ebd689ae136a762027033f
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29810
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This mainboard is based on mc_apl1. In a first step, it contains a copy
of mc_apl1 directory with minimum changes. Special adaptations for
mc_apl5 mainboard will follow in separate commits.
Change-Id: Icdbb116a822ffa7a3bfb7026a5d1164db56a0c46
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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