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path:
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src
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siemens
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mc_apl1
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variants
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mc_apl3
Age
Commit message (
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Author
2019-07-12
mb/siemens/mc_apl3: Enable LPSS UART 1
Mario Scheithauer
2019-07-11
mb/siemens/{baseboard,mc_apl3,mc_apl4,mc_apl5}: Fix GPIO_168
Mario Scheithauer
2019-07-11
mb/siemens/{mc_apl1,...,mc_apl5}: Reduce eMMC bus speed mode
Mario Scheithauer
2019-05-29
src/mainboard: Add missing 'include <types.h>'
Elyes HAOUAS
2019-04-15
mb/siemens/mc_apl1: Enable HDA in devicetree for all mainboard variants
Werner Zeh
2019-03-04
arch/io.h: Add missing includes
Kyösti Mälkki
2018-11-16
mb/siemens/mc_apl1/variants/mc_apl*: Remove unused BOARD_SIEMENS_MC_APL*_VAR
Elyes HAOUAS
2018-11-16
mb/*/*/Kconfig: Use CONFIG_VARIANT_DIR for devicetree
Peter Lemenkov
2018-11-12
siemens/mc_apl3: Disable PCI clock outputs on XIO bridges
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Set Full Reset Bit into Reset Control Register
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Set bus master bit for on-board PCI device
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Remove the correction of the Tx signal for SATA
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devices
Mario Scheithauer
2018-11-07
siemens/mc_apl3: Disable I2C7 over devicetree
Mario Scheithauer
2018-11-07
siemens/mc_apl3: Enable all PCIe root ports
Mario Scheithauer
2018-11-07
siemens/mc_apl3: Remove reduced clock rate for I2C0
Mario Scheithauer
2018-11-07
siemens/mc_apl3: Disable CLKREQ of PCIe root ports
Mario Scheithauer
2018-11-07
siemens/mc_apl3: Adjust GPIO settings for mc_apl3
Mario Scheithauer
2018-10-30
siemens/mc_apl3: Add new mainboard variant mc_apl3
Mario Scheithauer