coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2018-05-14	mb/scaleway/tagada: Update gpio configuration to use intelblock	Julien Viard de Galbert
	Update the gpio configuration structure to the intelblock format. The resulting configuration is functionally similar (even if some bits are not identical). Change-Id: Ide515424c6e1b0cb560b52a7f12909f23fd41e06 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/25424 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14	soc/intel/denverton_ns + mb: Rename gpio configuration	Julien Viard de Galbert
	In order to use the shared code in intelblock, this patch renames the denverton specific implementation to not use the same names (for files and types). - rename pad_config to remove conflict with soc/.../intelblocks/gpio.h - rename gpio.c, soc/gpio.h to not conflict with intelblock Note: There is no functional change in this patch. Change-Id: Id3f4e2dc0a118e8c864a96a435fa22e32bbe684f Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/24926 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-07	mb/scaleway/tagada: Add bmcInfo interface	Julien Viard de Galbert
	This interface gives access to configuration information stored in flash by the Tagada BMC before booting the SoC. Change-Id: I4351aa11b08bdf65e14706b261c532bbf8837aed Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-16	mb/scaleway/tagada: Update GPIO configuration	Julien Viard de Galbert
	Change-Id: Ia0293a0ec85c752686750dadb9730a159fd0c073 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-16	mb/scaleway/tagada: Remove memory down option	Julien Viard de Galbert
	The board does not have memory down, only 2 DDR4 Slots. Change-Id: I70eda83fbce7a707da170c7e555ed1a6dc6b1f4a Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-16	mb/scaleway/tagada: Copy intel/harcuvar and rename	Julien Viard de Galbert
	Change-Id: I6fc1f8393ce3f5ba6f52edad7cf8efa5524d2704 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>