| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2020-11-20 | mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes | Julien Viard de Galbert | |
| Change-Id: Ic3ed97fc2b54d4974ec0b41b9f207fe3d49d2cce Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> | |||
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index : coreboot.git | |
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