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2020-03-18mainboard/[^a-p]*: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I18e513cefc373b1cd70d31d1159928cc948a8476 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-03-03LGA1155 mainboards: Remove gfx.did and gfx.ndidAngel Pons
They are downright useless and result in ACPI errors. So, burn them. Also, do a minor update to autoport's README about these values. Change-Id: Idb5832cfd2e3043b8d70e13cbbe8bd94ad613120 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-01-05mb/sapphire/pureplatinumh61: Make devicetree prettierAngel Pons
Align contents, and fix some redundant comments. Change-Id: I0c9e98281aeb887308c3cbb421105b1faf922063 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-05mb/sapphire/pureplatinumh61/devicetree.cb: Drop zero valuesAngel Pons
They default to zero already. Change-Id: Ib888377f06d6fcb79cff5e30155971c17aa2597c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-09-30sb/intel/bd82x6x: Use common final SPI OPs setupArthur Heymans
This also reworks the interface to override OPs from the devicetree to match the interface in sb/intel/common/spi. Change-Id: I534e989279d771ec4c0249af325bc3b30a661145 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-19sb/intel/{bd82x6x|ibexpeak}: Drop p_cnt_throttling_supportedPatrick Rudolph
The processor P_BLK doesn't support throttling. This behaviour could be emulated with SMM, but instead just update the FADT to indicate no support for legacy I/O based throttling using P_CNT. We have _PTC defined in SSDT, which should be used in favour of P_CNT by ACPI aware OS, so this change has no effect on modern OS. Drop all occurences of p_cnt_throttling_supported and update autoport to not generate it any more. Change-Id: Iaf82518d5114d6de7cef01dca2d3087eea8ff927 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-24cpu/intel/model_206ax: Remove the notion of socketsArthur Heymans
With the memory controller the separate sockets becomes a useless distinction. They all used the same code anyway. UNTESTED: This also updates autoport. Change-Id: I044d434a5b8fca75db9eb193c7ffc60f3c78212b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31031 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23mb/*/*/devicetree.cb: Make sandybridge devicetree uniformArthur Heymans
This is a merely cosmetic change. Change-Id: If36419fbee9628b591116604bf32fe00a4f08c17 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-05-02mb/sapphire/pureplatinumh61: Use custom SPI OPMENUNicola Corna
The SPI chip in this board needs a custom OPMENU, otherwise flashrom fails halfway during the write. From the default OPMENU, Block Erase (0xd8) has been replaced by AAI write (0xad) and Fast Read (0x0b) by Write Disable (0x04). Change-Id: Ie18ee4e32511482dab747c9ffeac60d3994df320 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/25551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-04-13mainboard/sapphire/pureplatinumh61: Enable EuP and PMENicola Corna
With EuP and PME enabled the USB power turns off during S5. Change-Id: I8b9fd7bb308f544401f90f8aa5ffaec61251b2b3 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/19073 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-03-27mainboard: Add Sapphire Pure Platinum H61Nicola Corna
This board has a socketed SOIC-8 4 MB flash chip. All the flash regions are unlocked by default but unfortunately flashrom doesn't work with the original firmware and the stock UEFI flash tool refuses to flash the coreboot image (different image ID). For now, the external programmer seems to be the only option for the first coreboot flashing. Tested and working: * Debian GNU/Linux Stretch (with Linux kernel 4.9, SeaBIOS) * Microsoft Windows 7 installer with VGA blob (SeaBIOS) * Internal GPU, both with VGA blob and libgfxinit (VGA and DVI) * External GPU * RAM (tested 8 + 8 GB) * S3 * USB, both the 2.0 and 3.0 ports * Sata * Thermal management * Sound * LAN * Bluetooth * VT-x and VT-d * me_cleaner Not working: * Microsoft Windows 7 installer with libgfxinit Untested: * Backside Mini PCI-E port * DisplayPort and HDMI ports Issues: * The USB is always powered, even is S3 and S5 (like in the original firmware). * Internal flashing with flashrom doesn't work after resuming from S3. * The raminit is unreliable, as the RAM training sometimes fails and sometimes succeeds, with the same couple of RAMs. Once a MRC cache has been created, the raminit works fine. * If an external card is inserted and the option ONBOARD_VGA_IS_PRIMARY is not enabled, the internal GPU disappears completely from the PCI bus. Change-Id: I76aca2cfc4708c1728ae03ee4f6bc59d976c28a0 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/18564 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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