coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-11-01	soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi	Subrata Banik
2018-11-30	cpu/intel/common: Use a common acpi/cpu.asl file	Arthur Heymans
2018-11-23	mb: Set coreboot as DSDT's manufacturer model ID	Elyes HAOUAS
2018-11-21	ACPI: Fix DSDT's revision field	Elyes HAOUAS
2017-12-20	intel/bd82x6x: Use generated ACPI PIRQ	Tobias Diedrich
2016-07-30	chromeos mainboards: remove chromeos.asl	Aaron Durbin
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-10-22	gma ACPI: Make brightness levels a per board setting	Nico Huber
2015-10-14	sandy/ivy: Fix PIRQs on Chromebooks	Kyösti Mälkki
2015-06-24	sandy/ivy: Include IRQ routes from platform	Kyösti Mälkki
2015-05-26	bd82x6x: Merge common platform ASL code.	Vladimir Serbinenko
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2013-02-04	Intel based boards: Use tab instead of spaces to align comment in DSDT	Paul Menzel
2012-07-24	Move GGL0001 ACPI code to generic ChromeOS code	Stefan Reinauer
2012-04-30	Add support for Sandybridge base Samsung ChromeBox	Stefan Reinauer