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path: root/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
AgeCommit message (Expand)Author
2020-12-15mb/purism/librem_mini: Adjust PL1/2 levelsMatt DeVillier
2020-12-08mb/*: Remove SATA mode config for CNL based mainboardsFelix Singer
2020-12-08soc/intel/cannonlake: Align SATA mode names with soc/sklFelix Singer
2020-11-09mb/purism/librem_mini: Fix USB_OC mapping in devicetreeMatt DeVillier
2020-11-09mb/purism/librem_mini: drop PcieRpSlotImplemented from LAN PCIeMatt DeVillier
2020-11-09mb/purism/librem_mini: Update smbios_slot_desc for M.2/WLANMatt DeVillier
2020-11-09mb/purism/librem_mini: Fix PCIe clock source mapping in devicetreeMatt DeVillier
2020-11-04mb/purism/librem_cnl: Set SaGv to FixedHighAngel Pons
2020-11-04mb/purism_librem_mini: Add child device, slot descriptions to PCIe RPsMatt DeVillier
2020-11-04mb/purism/librem_mini: Reorganize devicetreeMatt DeVillier
2020-11-04mb/purism/librem_mini: drop unused HeciEnabled registerMatt DeVillier
2020-11-04mb/purism/librem_mini: Increase TDP/PL2 settingMatt DeVillier
2020-11-04mb/purism/librem_mini: Drop devicetree settings which default to 0Matt DeVillier
2020-11-04mb/purism/librem_mini: drop SendVrMbxCmd from devicetreeMatt DeVillier
2020-11-03mb/purism/librem_cnl: Adjust in preparation for new variantsMatt DeVillier
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-10 07:36:07 +0000