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2021-11-23mb/prodrive/hermes: Number Ethernet devicesAngel Pons
The Prodrive Hermes mainboard has four i211 Ethernet NICs and an i210 Ethernet NIC, but their numbering isn't consistent with the PCIe root port function numbers. With only a M.2 SSD plugged in, Linux uses the following names: PHY 0 ---> enp6s0 PHY 1 ---> enp4s0 PHY 2 ---> enp3s0 PHY 3 ---> enp1s0 PHY 4 ---> enp2s0 These names change after adding or removing PCIe devices in slots connected to root ports that get enumerated before the NICs' root ports, because the assignment of secondary bus numbers depends on the enumeration order. Because of this, the "predictable" network interface names are not at all predictable, which is awful. To avoid this, describe the NICs using SMBIOS Type41 entries with the correct instance numbers. With this patch, Linux uses these names: PHY 0 ---> eno0 PHY 1 ---> eno1 PHY 2 ---> eno2 PHY 3 ---> eno3 PHY 4 ---> eno4 No matter what PCIe devices are present, these names don't change. Change-Id: I7a527298f84172f9135006083ad7e748dcc27911 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58628 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-22mb/prodrive/hermes: Rename "internal audio" settingAngel Pons
The "internal audio connection" setting is actually about the front panel audio. Rename functions and variables to reflect this. Change-Id: I1be8f68ac3e8b91bc4983dc06daa37afb7bdf926 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin van Son <justin.van.son@prodrive-technologies.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-29mb/prodrive/hermes: Enable LTR for all PCIe portsAngel Pons
Set the `PcieRpLtrEnable` option to enable the LTR capability on all PCH PCIe root ports. TEST=Verify LTR capability enabled in `DevCap2` using `lspci -vv` Change-Id: I07ea37d178ea61d904c4f131fdea31479e899ef3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58326 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-29mb/prodrive/hermes: Map PCIe clocks to root portsAngel Pons
Map each PCIe clock source to the corresponding root port. Also, correct the CLKREQ# mapping for clock sources not associated to any CLKREQ# pin. The default `PcieClkSrcClkReq` value of 0 corresponds to CLKREQ# 0. TEST=Check that Linux sees the same PCIe devices with this commit: - All 5 onboard Ethernet NICs - BMC - Two random graphics cards in PEG0 and PEG1 slots - M.2 M NVMe SSD Change-Id: I0515877a36d42fb8858a0f0b3c0af1199a18d9af Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-29mb/prodrive/hermes: Fix PCIe ClkSrc configurationAngel Pons
Correct the PCIe clock source configuration as per the schematics. Apparently, FSP does not turn off unused PCIe clock sources when using SPS (Server Platform Services) firmware, but it does when using CSME firmware. TEST=BMC and Ethernet NICs get detected when using CSME firmware. Change-Id: Id25a34816f512510640db95251a7a792c1eebe62 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-26mb/prodrive/hermes: Remove overridetreeAngel Pons
There's no need to have an overridetree with a single board variant. TEST=Compare static.c and observe only device order has changed. Change-Id: I2097e247c27d5d0c5479cb533b477cd490a4c827 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-26mb/prodrive/hermes: Reorganize per-port PCIe settingsAngel Pons
Move per-port PCIe settings inside the corresponding PCIe root port device. Also, remove several unnecessary and/or redundant comments. Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical. Change-Id: I3f64d56b3b2c592194b18ae7b7c63ef41a1e060f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-08mb/prodrive/hermes: Enable SATA power optimizerAngel Pons
Enable SATA power optimizer as recommended by Intel. Tested, a SATA SSD is still detected correctly by SeaBIOS (version 1.14.1). Change-Id: Ia6d29de08583dfc0c2d38e8395adcaa2c540ec7b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-09-13mb/prodrive/hermes: Hook up P2SB and PMC in devicetreePatrick Rudolph
Fixes commit bd5b4aa683a634a73a6a63d1f197e2bb74b6a80e "soc/intel/cannonlake: Switch PMC to use device callbacks" as it requires the PCI device 1f.2 to be present in the devicetree. It was missing for this mainboard and caused a boot failure. Change-Id: Iaf508b2d955578efa2a266af50c568f5c0a47aaf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-09-03mb/prodrive/hermes: Do not overwrite `IedSize` UPDAngel Pons
SoC code already sets this UPD to `CONFIG_IED_REGION_SIZE`, which defaults to 0x400000 for soc/intel/cannonlake. Change-Id: I6587e17a4a3425c561cffe6e3df0d932a2458168 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-09-03mb/prodrive/hermes: Use `BOARD_TYPE_SERVER` defineAngel Pons
Change-Id: I291dc71bb6e3888b71ebce315f9ad09ccbc4a9a7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-08-28soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by defaultFelix Singer
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the default by changing its enum value to 0 and remove its configuration from all related devicetrees. If `common_soc_config.chipset_lockdown` is not configured with something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT` is used. Also, add a release note for the upcoming 4.15 release. Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-06mb/prodrive/hermes: Update HDA codec subvendor IDAngel Pons
Tested on prodrive/hermes. Change-Id: I72be8bde59d9eb0c1eff8c65dc734c6805732e09 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56086 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: <wouter.eckhardt@prodrive-technologies.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `VARIANT_DIR` onceAngel Pons
Specify the type of the `VARIANT_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: Iea2f992a59e41e00fec3cdc9d6a13b5f3ab0a437 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56558 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `OVERRIDE_DEVICETREE` onceAngel Pons
Specify the type of the `OVERRIDE_DEVICETREE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I4cbf4e318a30f0cf75aa8690e7454b9caa115c9d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56556 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_PART_NUMBER` onceAngel Pons
Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_DIR` onceAngel Pons
Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26src/*: Specify type of `CBFS_SIZE` onceAngel Pons
There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol more than once. This is done in `src/Kconfig`, along with its prompt. Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-01mb/prodrive/hermes: Implement smbios_mainboard_versionPatrick Rudolph
Return the HSI version read from BMC in smbios_mainboard_version. Change-Id: If907d598c9e05d35f8898d294678f61d075f935a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-16mb/prodrive/hermes: Use serial numbers from BMCAngel Pons
The BMC EEPROM layout has been updated to contain system and mainboard serial numbers. Use these values in SMBIOS Type 1 and Type 2 tables. Change-Id: I55b51a856b4ad28fd56b02015b2e1d49cd629735 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55275 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28mb/prodrive/hermes: Rename EEPROM access functionsAngel Pons
Change-Id: I84b9ef080f1ac91ea6f7273457b882677abf70d3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52885 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28mb/prodrive/hermes: Simplify `read_write_config` signatureAngel Pons
The `write_offset` parameter is always zero. Remove it. Change-Id: Ib63cb25904ad6c1c7424a9c01d8bf1e84c08453b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52884 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-13mb/prodrive/hermes: Disable ACPI S3 and S4 with SPSAngel Pons
Hermes can be used with either CSME or SPS firmware. However, the SPS (Server Platform Services) firmware does not support ACPI S3 and S4 sleep states, and coreboot should not report S3 and S4 as supported. Add a Kconfig option to be selected when building coreboot to use with SPS firmware, which allows disabling ACPI S3 and S4 sleep state support. Change-Id: I9d0fa8530e198e86415f92da6719d2fb0d2401ec Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-28mb/prodrive/hermes: Drop Vref configuration for older boardsPatrick Rudolph
Drop Vref verbs from the baseboard table as it's not required for Rev. 3 and earlier. Change-Id: I41c207f97dad6c9107c1999eb46d2d6304a6c217 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-04-22soc/intel/cannonlake: Set DIMM_SPD_SIZE to 512Felix Singer
All related mainboards are setting DIMM_SPD_SIZE to 512. Therefore, default to 512 in the SoC Kconfig and drop it from related mainboard Kconfigs. Change-Id: Idb6a0e42961eeb490afd76b4aa7d940961991733 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52513 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-20mb/prodrive/hermes: Fix HSI versionPatrick Rudolph
Fix board ID (HSI) read from BMC: * R02 and R03 have an HSI of 2. * R04 has an HSI of 3. Change-Id: I987b2dd848c48e3562bcc07270c958cde3c5a962 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51920 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-17mb/prodrive/hermes: Fix SSDT MPTSPatrick Rudolph
MPTS is currently not executed by the AML interpreter. Use Method (\\_SB.MPTS) instead of Scope (\\_SB) Method (MPTS) ScopeEnd Tested on Prodrive Hermes. MPTS is now executed at S5. Change-Id: I9074eb4ba55aab3f9a47ae5e3c3ddd338406a5e4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: <wouter.eckhardt@prodrive-technologies.com>
2021-04-10mb/prodrive/hermes: Fix eeprom readingArthur Heymans
The logic for bytes to copy to the function input pointer was wrong. What it did was to loop over all 2 bytes that need to be read and only copy the first byte. Change-Id: Ic08cf01d800babd4a9176dfb2337411b789040f3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-04-06mb/prodrive/hermes: Properly pack EEPROM structuresAngel Pons
To pack a struct, the `__packed` attribute must come after the `struct` keyword. Moreover, unions cannot be packed (structs inside unions can, though). Correct uses of `__packed` so that EEPROM structs get packed. Change-Id: I39d2c9ebc370605d5623b134189aa95a074ec7c3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: <wouter.eckhardt@prodrive-technologies.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-03-18mb/prodrive/hermes: Disable HDA codec Port E by default on R04+Angel Pons
If the board settings aren't valid, Port E uses the settings for earlier board revisions, which is undesired. Disable Port E by default on R04+. Change-Id: I03bd50b915a2120283b77179debaa735bb7ef027 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51529 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/prodrive/hermes: Drop AZALIA_PLUGIN_SUPPORTPatrick Rudolph
Already selected by SoC. Change-Id: I1d941881f50350b6b581416a2e722ea2e7485a1c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-24mb/prodrive/hermes/hda_verb: Update verb table for latest board revisionPatrick Rudolph
Use different verb tables depending on board revision. For board revision R03 and older use the existing verb tables. For revisions newer than R03 use the new verb tables and also apply the dynamic audio configuration recently added. Also do the following: * Use correct NID port mapping * Fix verb count in ALC888 header * Fix NID in Intel codec verbs Change-Id: I24ea9149eb2cddb815ff82744a351c926a94aaef Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-24mb/prodrive/hermes/mb: Update SoC config in PRE_DEVICEPatrick Rudolph
As one option is consumed by MPinit, update the soc config even earlier. Tested on Prodrive hermes: Turbo can be disabled and cores won't exceed their base frequency. Change-Id: I9f444c3b91d2ee1a613ebac1922f1e6b60363c0b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-19mb/prodrive/hermes/eeprom: Add function to read HSI from EEPROMPatrick Rudolph
Will be used to determine the board revision. Change-Id: I41e4c6ad83e23c9d79e6abab3f38ad46bd3bec06 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50788 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19mb/prodrive/eeprom: Add BMC settingsPatrick Rudolph
Add settings describing the BMC. Will be used by the following patch to read the board revision. Change-Id: If464138fc1bdf02a45a21f638b179048d68d974d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50787 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-17mb/prodrive/hermes: Write board layoutPatrick Rudolph
The I2C EEPROM on SMBUS needs to be updated with the current board layout, so that the BMC knows the actual configuration. Collect all needed information and update the EEPROM if something changed. Every byte written add a delay of 5 msec. Change-Id: Ic8485e6c700eede75b1e829238ee70da65118ace Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-16mb/{intel,prodrive,protectli}: Remove unused <string.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<' Change-Id: Id2aa085a4762355d9fb1628df40f7b43fbc81fc0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-16mb/prodrive/hermes: Improve board config EEPROM handlingAngel Pons
* Check and print errors returned from reading from I2C * Rework offset calculation by using more macros * Get rid of stage-specific preprocessor code * Define the EEPROM layout as struct * Make use of the defined EEPROM layout to calculate offsets * Read the UPD to disable VT-d from EEPROM Change-Id: Iad77811318c7dfd3a3a4f8d523cfa0f457f168b6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48808 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/prodrive/hermes: Set Port C VREF as per EEPROM configAngel Pons
Configure Port C VREF according to the settings in the EEPROM. Change-Id: I5b4f0d91fc30c6b585434b9450544281f4411ff4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50396 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/prodrive/hermes: Configure 'internal audio'Angel Pons
Implement `mainboard_azalia_program_runtime_verbs` to configure the Realtek ALC888 codec according to the settings in the EEPROM. The encoding of the `internal_audio_connection` field is: 0: Disabled 1: Front HP out 2: Internal speaker Change-Id: I5e0013217838888977aaa9259e0cfb78c82f719f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-10mb/prodrive/hermes: Set mb_hda_amp_enable based on cfgPatrick Rudolph
Change-Id: I13c2ece729128fe245de88c0d36ce7b4bcaf6b6d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10mb/prodrive/hermes: Drop reset functionsPatrick Rudolph
The reset GPIOs are already configured in bootblock. Drop the unused ramstage code. Change-Id: Ic99fcae2a3f00be7eebd7be618df838522dac69f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-04mb/prodrive/hermes: Use some board settings from EEPROMAngel Pons
Cache the board settings in memory to avoid having to read them from the EEPROM multiple times. For now, configure the following settings: - DeepSx - USB power in S5 - Power state after G3 Change-Id: Id88529a0b064c54fdf341de3856a8877109d4b14 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-04mb/prodrive/hermes: Define board settings in EEPROMAngel Pons
Hermes has an EEPROM with firmware configuration data. Add definitions to read and verify the `board settings` from the EEPROM. Subsequent commits will hook up these EEPROM settings. Change-Id: Id86632192ae53fd6b0e4df5b26b5a0a81e972818 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-01-27ACPI: Add top-level ASLKyösti Mälkki
Objects that are created with acpigen need to be declared with External () for the generation of dsdt.asl to pass iasl without errors. There are some objects that are common to all platforms, and some that should be declared only conditionally. Having a top-level ASL helps to achieve this. Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-22mb/prodrive/hermes: Fix 30 second boot delayPatrick Rudolph
The PMC doesn't response any more due to invalid CNVi GPIO configuration. This caused a 30 second boot delay in FSP-S. Use the same values as FSP-S does. Always disable external I2S BT audio and use NF3 for pad GPP_D5 and GPP_D6. Tested on Prodrive hermes: No boot delay can be observed any more. Change-Id: I6f4a954786ec21512b0dce908d333952e96de048 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49678 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-20mb/prodrive/hermes: do UART pad configuration at board-levelMichael Niewöhner
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to the early UART gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Change-Id: I5b99a66fb64683f3647ebff3ab01ceb52058f79c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-24mb/prodrive/hermes: Drop EEPROM address function parametersAngel Pons
Only one EEPROM is used to store the board settings, and its I2C address is constant. Thus, there's no need to pass its address as a parameter. In addition, reduce the scope of the `I2C_ADDR_EEPROM` definition, since using it outside of eeprom.c would bypass the API's abstraction layer. Change-Id: I958304e6ed6df05af923139d44ff4fd1de204738 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-24mb/prodrive/hermes: Use already-defined SMBus macrosAngel Pons
Drop chipset register definitions in mainboard code in favor of existing definitions in a header. These definitions are not mainboard-specific. Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical. Change-Id: I29d6f35ec27bff43cf52ae697e905b6a7b48a8d1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-21mb/prodrive/hermes: Update USB 2.0 settingsAngel Pons
Test results show that USB signals look better with these settings. Yes, there's a macro in the devicetree now. All ports use the same settings except for the overcurrent pin, so this avoids redundancy. Change-Id: Ib0dafab88d8dcc05388b724f6a7183c13ac64934 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48694 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-21mb/prodrive/hermes: Enable S3/S4 resumePatrick Rudolph
Change-Id: I75f83bcc6c65a048e87f7295a66526eb384afc5d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-17soc/intel/cannonlake: Change mainboard_silicon_init_params argumentPatrick Rudolph
Use FSPS_UPD instead of FSP_S_CONFIG as argument as already done on xeon_sp and denverton_ns. This allows to set test config UPDs from mainboard code as well. Change-Id: I6d67264e22df32b9210ce88b99d6a7a4f6b97ffb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-12-14mb/prodrive/hermes: Update PCIe slots in devicetreePatrick Rudolph
* Drop PcieRpSlotImplemented on internal slots * Add PCIe port 15 that connected to CNVi/M.2 E Change-Id: Iaa05affa760b447fc1725e674b12366684a63720 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-05mb/prodrive/hermes: Generalise `check_signature` functionAngel Pons
Allow to specify which signature is to be checked. Change-Id: Ica874b1c4283fdb8dbd702c34ccb3315a2cf160d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-11-30mb/prodrive/hermes: Use PCH_DEV_SMBUS definitionAngel Pons
This allows dropping ugly preprocessor usage from this file. Change-Id: Idb66d295129d98725f38d11ac162978418bd94c2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-11-30mb/prodrive/hermes: Encapsulate GPIO setupAngel Pons
Having variants' gpio.c call the `gpio_configure_pads` function results in an API that does not need to pass data around, which is much simpler. Change-Id: I1064dc6258561bcf83f0e249d65b823368cf0d31 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-11-30mb/prodrive/hermes: Use C-style commentsAngel Pons
Most of the existing comments are C-style already. Change-Id: I9ca4779f5b0560320e9bce4f33e54766522689f9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-11-13soc/intel/cnl: replace the remains of HeciEnabled by device state in dtMichael Niewöhner
The option `HeciEnabled` was partly replaced by use of the device on/off state in the devicetree in commit 3de90d1. The option has been removed from the corresponding boards, so `HeciEnabled` is always 0 and ME always gets disabled during soc finalize, when `HECI_DISABLE_USING_SMM` is set. Replace the option in the finalize function by the same dt state check that sets the FSP option and drop the remaints of `HeciEnabled`. Devicetrees still having `HeciEnabled` have been adapted to keep the current behaviour. Change-Id: Ib4cca9099b9aa3434552a41fbafca7cf6a0dd0eb Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47195 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09soc/intel/*/chip: Remove unused devicetree entryPatrick Rudolph
InternalGfx isn't used so drop it. Change-Id: I12f424d8d883e065ef8d007e56a8bff41a7fae53 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-04mb/prodrive/hermes: Set tcc offset to 1Patrick Rudolph
Prevent early throttling when the ambient temperature is high. Change-Id: Ie6881c9c0942aae3e43509170352271a74244d42 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-02mb, soc/intel: Reorganize CNVi device entries in devicetreeFurquan Shaikh
This change reorganizes the CNVi device entries in mainboard devicetree/overridetree and SoC chipset tree to make it consistent with how other SoC internal PCI devices are represented i.e. without a chip driver around the SoC controller itself. Before: chip drivers/wifi/generic register "wake" = "..." device pci xx.y on end end After: device pci xx.y on chip drivers/wifi/generic register "wake" = "..." device generic 0 on end end end Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-10-26mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`Michael Niewöhner
The dt option `speed_shift_enable` is obsolete now. Drop it. Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-10-21soc/intel,mb/*: get rid of legacy pad macrosMichael Niewöhner
Get rid of legacy pad macros by replacing them with their newer equivalents. TEST: TIMELESS-built board images match Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-13{src/mb,util/autoport}: Use macro for DSDT revisionElyes HAOUAS
Change-Id: I5a5f4e7067948c5cc7a715a08f7a5a3e9b391191 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-10-13mb, soc/intel: Switch to using drivers/wifi/generic for Intel WiFi devicesFurquan Shaikh
This change switches all mainboard devices to use drivers/wifi/generic instead of drivers/intel/wifi chip driver for Intel WiFi devices. There is no need for two separate chip drivers in coreboot to handle Intel and non-Intel WiFi devices since the differences can be handled at runtime using the PCI vendor ID. This also allows mainboard to easily multi-source WiFi chips and still use the same firmware image without having to distinguish between the chip drivers. BUG=b:169802515 BRANCH=zork Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-05soc/intel/common/block/acpi: Factor out common platform.aslSubrata Banik
This patch moves platform.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CNL and CML platform. 1) Dump and disassemble DSDT, verify _PIC method present inside common platform.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I5189b03d6abfaec39882d28b40a9bfa002128be3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-22mb/*: drop GENERIC_SPD_BIN from boards without soldered memoryMichael Niewöhner
Drop GENERIC_SPD_BIN from boards selecting it, despite having no soldered memory. Change-Id: Id05fe45007d5662ff9bee326f28470df1206fcff Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45146 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-06mb/*: devicetree: drop now unneeded USBx_PORT_EMPTYMichael Niewöhner
Setting USBx_PORT_EMPTY is not a requirement anymore, since unset devicetree settings default to 0 and the OC pin now only gets set when the USB port is enabled (see CB:45112). Thus, drop the setting from all devicetrees. Change-Id: I899349c49fa7de1c1acdca24994ebe65c01d80c6 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-09-04soc/intel/cnl: Enable HECI3 depending on devicetreeFelix Singer
Currently HECI3 gets enabled by the option Heci3Enabled, but this duplicates the devicetree on/off options. Therefore depend on the devicetree for enablement of the HECI3 controller. All corresponding mainboards were checked if the devicetree configuration matches the Heci3Enabled setting, and divergent devicetrees were adjusted. Change-Id: Ic7d52096aee225c2ced1e1bc29ca850fe5073edc Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44579 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24mb/prodrive/hermes: Remove duplicate entry from devicetreeFelix Singer
Change-Id: Iad0b28d5ad8339efd5a6055abfd7ced074d248b1 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44692 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-23soc/intel/cnl: Configure FSP option PcieRpSlotImplementedNico Huber
Allow configuring FSP option PcieRpSlotImplemented. Also, update all related devicetrees and configure PcieRpSlotImplemented to keep the current behaviour. Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-08-23mb/prodrive/hermes: Add root port numbers to commentsFelix Singer
Change-Id: I06bb0493999f1f6954854f872cda46dc38930370 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-08-18mb/prodrive/hermes: Enable LPSS ACPI driverPatrick Rudolph
Enable the introduced LPSS ACPI uart driver. Tested on Hermes using Linux 5.6: The UART2 appears as /dev/ttyS2. Change-Id: Ic15be4a807012216e52c848120de7e39522f57b7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-12mb/prodrive/hermes: Add multifunction device for UART 2Christian Walter
On CNP-H, only four I2C controllers are available, so PCI devices 19.0 and 19.1 are missing. However, PCI device 19.2 still exists as UART 2. That function 0 is missing means UART 2 can only be used in ACPI mode. Both devices need to be marked as hidden on the devicetree so that the allocator takes UART 2 into account. Change-Id: Ie77198cc0327414b9f88cf15ba4efaddb4f5cca4 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-08-04mb/**/{devicetree,overridetree}.cb: Indent with tabsAngel Pons
Use tabs instead of eight (sometimes less) spaces. Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-28mb/prodrive/hermes: Relocate device enable optionsFelix Singer
Since there aren't any other variants, we can move things between the devicetree and the overridetree. Built with BUILD_TIMELESS=1, resulting coreboot.rom does not change. Change-Id: I54aac67237a3850dbf11f58bd41aba87505214f3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43927 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28mb/prodrive/hermes: Add ME interface numbers to commentsFelix Singer
Change-Id: Ief8d53b79918d4d68bf10650ff796a27b67d862b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43921 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23mb/prodrive/hermes: Update VBT fileChristian Walter
Update .vbt file to support two DP outputs. Change-Id: Ifd4163aafe4ef3070d04a72a4699303af72c5102 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-12mb/prodrive/hermes: Deselect PCIEXP_CLK_PM and L1_SUB_STATEChristian Walter
Set default of PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE to n as this breaks booting Windows with a PCIE NVIDIA. Change-Id: Ie8768b91c27c4159f9b3c7f94699134a82decea0 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-07-01mb/prodrive/hermes/variants/baseboard: configure sataHotplugJonas Loeffelholz
Configure sataHotPlug in devicetree, as this functionality is now available for this soc. Change-Id: If462e33d1bbef8036d598970fb2774d0fda1fbb1 Signed-off-by: Jonas Loeffelholz <Jonas.Loeffelholz@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42804 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30src: Remove whitespaces before tabsElyes HAOUAS
Change-Id: I73695152ec8d8ab2dabf8421ef2405f70de0f4ba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42795 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-26mainboard/prodrive/hermes: Enable EIST in DeviceTreeChristian Walter
Enable EIST option in the devicetree in order to make Windows aware of using Intel CPU Turbo Technology. Change-Id: Ied3d7e934fcab2d5d491573245d68d392df5ba34 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-22mb/prodrive/hermes: Disable xDCIPatrick Rudolph
The PCI device is used for debugging only and as Windows 10 has no default driver for it, disable it to not scare end users about "missing" drivers. Change-Id: I0b42a9b55f00826c5920c1c259b38382bdcdde72 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42509 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-19Kconfig: Escape variable to accommodate new Kconfig versionsPatrick Georgi
Kconfig 4.17 started using the $(..) syntax for environment variable expansion while we want to keep expansion to the build system. Older Kconfig versions (like ours) simply drop the escapes, not changing the behavior. While we could let Kconfig expand some of the variables, that only splits the handling in two places, making debugging harder and potentially messing with reproducible builds (e.g. when paths end up in configs), so escape them all. Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-06-06mb/prodrive/hermes: Add new mainboard portChristian Walter
This patch adds support for the Prodrive Hermes mainboard. Tested with CoffeeLakeFspBinPkg FSP 7.0.68.41. Untested: * CNVi * Intel Graphics Tested: * CPU Intel Xeon E2288G * CPU Intel Core i3-9100F * CPU Intel Core i7 9700KF * CPU Intel Core i7 9700E * CPU Intel Core i7 9700F * CPU Intel Core i5 9600K * CPU Intel Pentium Gold G5400 * PCIe Link Width x8 on Slot6 by changing PCIe mux * All four DDR4 slots in different configurations * USB2.0 HDR1 * USB2.0 HDR2 * USB3.0 HDR * Slot1 * Slot2 * Slot3 * Slot4 * Slot6 * M2.M NVMEe * Ethernet PHYs 0-4 * Aspeed BMC PCIe * Aspeed BMC USB * Aspeed Graphics init * USB3 backplane all working * I801 SMBUS Not Working: * Intel HDA Change-Id: Id7d051d3fa6823618691d5572087c9ae589c2862 Signed-off-by: Christian Walter <christian.walter@9elements.com> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-12 05:41:00 +0000