| Age | Commit message (Collapse) | Author |
|---|
|
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I7c50f770c3a7ab261d6ea41f945e2239ba53fd09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Ia5b6c5c72a1eafe1118e92e4579decb4f4abc9e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
commit c6b041a12e refactor the TPM Kconfig. MAINBOARD_HAS_LPC_TPM
has changed to MEMORY_MAPPED_TPM.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Iff7e20ac271eb5b2afc9061819e2cc0cf2264cbf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63773
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable SPI dTPM using eSPI bus.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I18ca41c143ade024ee2840b619ba777b22a2a86a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Update Kconfig per Atlas usages:
1. Set EC I/O mapped UART as default UART output
2. Add EC IFD region & ACPI support
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I970de724237bcb08899aed7a4b87a23c5cdb0b48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
|
|
This is a initial mainboard code cloned from adlrvp aimed to serve as
base for further mainboard check-ins. This commit copies the mainboard
directory and adjusts the naming to match the new board's name.
Besides, This commit also trims down major parts of adlrvp code except
some of ADL-P DDR5 RVP as Atlas is using it as main reference.
Follow-up commits will introduce the needed changes for the new
mainboard.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Ia3129f68c73969604edcd290c3e50ad219cf88d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60899
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
