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path: root/src/mainboard/prodrive/atlas/Kconfig
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2024-04-30soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZEFelix Singer
Alderlake and Raptorlake SoCs support DDR4 and DDR5, which have a total SPD size of 512 bytes. Set this as the default and remove the setting from mainboard Kconfigs. Change-Id: I8703ec25454a0cd55a3de70f73d2117285a833ae Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82115 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18mb/opencellular to mb/roda: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Ia2100d26027a7f71739d5445f781b52c517ed966 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80594 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-10-03mb/prodrive: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: Iface0fd1d44649c6d9773940818e028e3d3a4292 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-04-19soc/intel/alderlake: Rename SOC_INTEL_ALDERLAKE_S3 to D3COLD_SUPPORTSean Rhodes
The Kconfig option SOC_INTEL_ALDERLAKE_S3 suggests that it's doing something with S3, but it's actually disabling D3Cold support. Rename it to D3COLD_SUPPORT to make it clear what it's doing. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ifc3f19912ac7ee55be8ec7a491598140f9532675 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-04-12Revert "soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT"Michael Niewöhner
This reverts commit 6bfca1b689e48be4f72e8fa401f3558d845fc282. Reason for revert: dependency for revert CB:73903 Change-Id: I56bab4d85d04e90cacfe77db59d0cde6a8a75949 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-21mb/prodrive/atlas: Configure PCIe CLKREQMaximilian Brune
Intel Client PCIe* controller expects each device should drive the SRCCLKREQ#. If the GPIO is set to native mode for a device, which does not support SRCCLKREQ#, then during RTD3 exit link would not be established. Because controller samples the SRCCLKREQ# before detecting the device and break L1 as the system might enter L1SS as controller detects SRCCLKREQ# as de-asserted. As a workaround the Pins must not be configured in Native Mode (CLKREQ native function). Therefore here they are not configured at all. source: 689882 (intel document ID) So apparently hardware doesn't sample SRCCLKREQ Pin if it's not configured as such. That workaround suggestion however also brought a patch to FSP, which in turn causes the same bug (even if SRCLKREQ are not configured). Usually in order to make use of root port power saving features (e.g. clock gating), the Root port must either be disabled or a CLKREQ Pin must be configured. The patch however removed that check before enabling power management for the rootport. Workaround (until FSP is fixed): pretend to FSP that the rootports have a CLKREQ Pin attached, by supplying them in the FSP UPDs. That will cause FSP to configure the CLKREQ Pin and enable power management for said rootport, but it will not crash on L1 entry/exit. That has been done on the Atlas board (as workaround) for a short period of time (before applying FSP Fix) like this: // RP 5 (the rootport you want to fix) - memupd->FspmConfig.PcieClkSrcUsage[2] = 4; // e.g. choose a clkreq pin that is not routed out - memupd->FspmConfig.PcieClkSrcClkReq[2] = 0; Furthermore disable CpuPcieRpClockReqMsgEnable FSP-M options to prevent the same issue, but for CPU root ports. If not done the following will happen in coreboot: [DEBUG] PCI: 00:06.2 scanning... [SPEW ] do_pci_scan_bridge for PCI: 00:06.2 [DEBUG] PCI: pci_scan_bus for bus 02 [DEBUG] PCI: 02:00.0 [1344/5410] enabled [INFO ] PCIe: Common Clock Configuration already enabled [INFO ] PCIE CLK PM is not supported by endpoint [INFO ] ASPM: Enabled L1 [EMERG] CPU Index 9 - APIC 32 Unexpected Exception:18 @ 10:76aeb93f - Halting [EMERG] Code: 0 eflags: 00000046 cr2: 00000000 [EMERG] eax: 00000000 ebx: 00000009 ecx: 00000000 edx: 00000000 [EMERG] edi: 00000009 esi: 76b218c4 ebp: 00000000 esp: 76b29100 [EMERG] 0x76aeb8f8: c4 2c 5b 5e 5f 5d c3 56 [EMERG] 0x76aeb900: 53 83 ec 14 65 a1 00 00 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: If2acdc16f37cdae0292f55d210b058f82179bfb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-02-20soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORTSean Rhodes
Select NO_S0IX_SUPPORT for `starlabs/starbook` and `atlas/prodrive` so their configurations are unchanged. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I718952165daa6471f11e8025e745fe7c249d3b46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72800 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-25mb/prodrive/atlas: Disable SaGv by defaultLean Sheng Tan
Customer needs SaGv to be disabled by default. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I8454c267dcc12d2ef7de7bd23296a17294f058a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2022-12-02mb/prodrive/atlas: Enable GPP_B14 buzzer supportLean Sheng Tan
Per Intel doc 621483, 26.1.1 - NMI_STS_CNT, 8254 timer is required for Speaker Data output (buzzer) at GPP_B14 NF1, as it is using 8254 timer counter 2 output. However when 8254 timer is used, S0ix will not work as 8254 has to be gated instead. For further info on s0ix requirements, refer to Intel doc 610002 (Modern Standby Unified Checklist). This CL also disables s0ix because it is not required by the platform. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ib5e7787a47509ed09818d8515d21a80196fb1ec6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67553 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-04mb/prodrive/atlas: Add IBECC Kconfig optionMaximilian Brune
Add an option on Atlas to enable IBECC (In Band Error Correction Code), which is currently needed for endurance testing. Test: start atlas mainboard with Linux. See in dmesg that IBECC (EDAC igen6) driver is loaded. Inject a fake error via debugfs and see in dmesg that Linux handles it. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I71ee2401136e2dc70b3164db6c99af03a3e1f346 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-26mb/prodrive/atlas: Disable S3Maximilian Brune
The Atlas board has currently the problem that suspending the System causes the System to freeze. Therefore disable S3, until the cause is figured out and fixed. Change-Id: I5b28787df9b01683fcd4a1de8267840a80bb4fe6 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68591 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-30mb/prodrive/atlas: Add Kconfig option to enable SaGvLean Sheng Tan
It turns out that one can use Kconfig options to specify values for devicetree options, as long as the resulting expression is a compile time constant. Use this to configure SaGv for Atlas: enable it by default, but allow SaGv to be disabled manually for convenience when testing. Enabling SaGv makes MRC train the RAM multiple times, which takes a significant amount of time. For further info on SAGV on ADL, please refer to Intel Doc 655258 (Alder Lake Datasheet) section 5.1.3.2. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Change-Id: I3c6ac25d414122c408f2348d12dba8dce909e567 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-13mb/prodrive/atlas: Enable legacy S3 supportLean Sheng Tan
Enable S3 support as Prodrive doesn't need s0ix for now. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I7625c8ac860e1afc60c94b3c51e996531a1f2b15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67414 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-09-09mb/prodrive/atlas: Enable resizable BAR supportLean Sheng Tan
Allow up to 4GiB resizable BAR support. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I097483ba8b4479211f67f29a42754d1a51379771 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-08mb/prodrive/atlas: Disable POST codes by defaultLean Sheng Tan
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ib1dd9826cedfd0a3f1ed719cf2e2927f09f783fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/67427 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-03mb/prodrive/atlas: Select FSP_TYPE_IOTLean Sheng Tan
Atlas uses IoT FSP. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I4c20600e0b62367e6e58908cf9cf916f309e6362 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-07-20mb/prodrive/atlas: Swtich from EC UART to LPSS UARTLean Sheng Tan
Switch x86 uart output from EC to LPSS. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I2756d139a72185ba6a5c6d1079d770ce33afdf71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65985 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-05mb/prodrive/atlas: Increase CBFS size to 8MBLean Sheng Tan
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I7c50f770c3a7ab261d6ea41f945e2239ba53fd09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-05mb/prodrive/atlas: Add data.vbt for 4 DPs supportLean Sheng Tan
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ia5b6c5c72a1eafe1118e92e4579decb4f4abc9e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-04-22mb/prodrive/atlas: Fix build errorEric Lai
commit c6b041a12e refactor the TPM Kconfig. MAINBOARD_HAS_LPC_TPM has changed to MEMORY_MAPPED_TPM. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Iff7e20ac271eb5b2afc9061819e2cc0cf2264cbf Reviewed-on: https://review.coreboot.org/c/coreboot/+/63773 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-20mb/prodrive/atlas: Enable SPI TPM 2.0Lean Sheng Tan
Enable SPI dTPM using eSPI bus. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I18ca41c143ade024ee2840b619ba777b22a2a86a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-14mb/prodrive/atlas: Update KconfigLean Sheng Tan
Update Kconfig per Atlas usages: 1. Set EC I/O mapped UART as default UART output 2. Add EC IFD region & ACPI support Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I970de724237bcb08899aed7a4b87a23c5cdb0b48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-01-12mb/prodrive/atlas: Add new mainboard based on adlrvpLean Sheng Tan
This is a initial mainboard code cloned from adlrvp aimed to serve as base for further mainboard check-ins. This commit copies the mainboard directory and adjusts the naming to match the new board's name. Besides, This commit also trims down major parts of adlrvp code except some of ADL-P DDR5 RVP as Atlas is using it as main reference. Follow-up commits will introduce the needed changes for the new mainboard. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ia3129f68c73969604edcd290c3e50ad219cf88d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60899 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 05:51:41 +0000