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SPD data needs to remain within same chip -block
with device 0:18.2.
Change-Id: Ic12481b637ee5f5119faec3239b477f613e4e511
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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IOMMU was tested on Xen 4.8 and Linux kernel 4.14.33. Following feature
set is enabled:
(XEN) AMD-Vi: Disabled HAP memory map sharing with IOMMU
(XEN) AMD-Vi: IOMMU Extended Features:
(XEN) - Peripheral Page Service Request
(XEN) - Guest Translation
(XEN) - Invalidate All Command
(XEN) - Guest APIC supported
(XEN) - Performance Counters
(XEN) AMD-Vi: IOMMU 0 Enabled.
Change-Id: I6dbfae78849248f3532caa78974c8f2ce61a530d
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/26116
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is no physical LPC connector on apu3 mainboard. This board
contains only LPC debug test points with not all required pins exposed.
Change-Id: I83de16bb651846340788c6fa52c04b8e09e46a99
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/22630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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apu4 is new version of PC Engines platform, which contains 4 Ethernet
ports and 4GB of RAM. In functional way it is very similar to apu3.
Platform tested with booting Linux voyage (kernel 3.16.7) using USB and
SeaBIOS as 1st stage and GRUB as 2nd stage bootloader. Also Debian
(kernel 4.8.5) using iPXE.
Change-Id: Ia7a9971d25d4ecc215c392be1e46dc1c10129ba7
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/22629
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Apu3 and apu5 are additional variants of apu2 board.
Apu3 has no LPC connector exposed, but has additional USB header. It has
also 2 slots for SIM cards and one of the gpios is used to control
switching between them.
Apu5 is differing by having 6 SIM card slots (3 SIMSWAP switches).
This patch adds support for those other variants by not introducing
additional code redundancy.
Change-Id: I4fded98fed7a8085062cdea035ecac3d608cd2a0
Signed-off-by: Kamil Wcislo <kamil.wcislo@3mdeb.com>
Reviewed-on: https://review.coreboot.org/21981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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