coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2017-10-20	mainboard/pcengines/apu2: add apu3 and apu5 variants	Kamil Wcislo
	Apu3 and apu5 are additional variants of apu2 board. Apu3 has no LPC connector exposed, but has additional USB header. It has also 2 slots for SIM cards and one of the gpios is used to control switching between them. Apu5 is differing by having 6 SIM card slots (3 SIMSWAP switches). This patch adds support for those other variants by not introducing additional code redundancy. Change-Id: I4fded98fed7a8085062cdea035ecac3d608cd2a0 Signed-off-by: Kamil Wcislo <kamil.wcislo@3mdeb.com> Reviewed-on: https://review.coreboot.org/21981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-29	AGESA binaryPI: Drop amdlib.h in BiosCallouts.c	Kyösti Mälkki
	Some fam14 boards will need more work on this area, those are to be addressed with followup patches. Change-Id: I14208cf8519a4cf71e4944d08a2dae36b7f1f878 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-12	AGESA boards: Clean up Ids.h and Filecode.h includes	Kyösti Mälkki
	Change-Id: I9cb63ff58900a39d7cd8e3da2b9a9a95c2a41a69 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-12	AGESA boards: Drop heapManager.h includes	Kyösti Mälkki
	Change-Id: I1a96b1c6181cd657d7aee82370ef86acd688cc94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25	amd/pi/hudson: Move oem_fan_control()	Martin Roth
	It was not intentional to change oem_fan_control() to non-static with commit 23e5ba9 binarypi mainboards: Clean up IS_ENABLED fan control Every platform except bettong had its own static version of oem_fan_control, so remove the definition of oem_fan_control from imc.h, and move it out of imc.c into bettong's BiosCallOuts.c. Change-Id: Ie95ac1fd3a57259bb35796903aa8753ef0e70d70 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21189 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-24	binarypi mainboards: Clean up IS_ENABLED fan control	Marshall Dawson
	Remove all checks for #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) around the imc.h includes. Convert from #if to if() for all fan control setup code. Where necessary, make functions non-static to match the prototypes in imc.h. Change-Id: If88af42d00227285931829441909a982fc292b2b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-07-17	binaryPI: Switch to agesa/def_callouts.c	Kyösti Mälkki
	Change-Id: Id20a49385aeb336461acd0bd186a4ab7f3fb95b8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-07-17	binaryPI: Switch to agesa/heapmanager.c	Kyösti Mälkki
	Essentially squashes following commits from AGESA side. 45ff9cb AGESA: Reduce typecasting in heapmanager calls bceccec AGESA: Handle HEAP_CALLOUT_RUNTIME allocation more cleanly 4240277 AGESA: Adjust heap location for S3 resume path 424c639 AGESA: Refactor S3 support functions 50e6daf AGESA: Log heap initialisation da74041 AGESA: Move heap allocator declarations c74b53f AGESA: Reduce SPI use by 24kB for S3 support b1fcbf3 AGESA: Separate HeapManager declarations from BiosCallOuts f728408 AGESA: Split S3 backup in CBMEM 82fbda7 AGESA: Use same HeapManager for all BiosCallOuts Change-Id: I537bd05a3e06ff6896f1ac8be93eed5321ca472b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27	vendorcode/amd: Unify Porting.h across all targets	Stefan Reinauer
	This requires to also unify the calling convention for AGESA functions from AGESA_STATUS (agesa_func)(UINT32 Func, UINT32 Data, VOID ConfigPtr) to AGESA_STATUS (agesa_func)(UINT32 Func, UINTN Data, VOID ConfigPtr) On systems running 32bit x86 code this will not make a difference as UINTN is uintptr_t which is 32bit on these machines. Change-Id: I095ec2273c18a9fda11712654e290ebc41b27bd9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-02-10	ddr3 spd: move accessor code into lib/spd_bin.c	Patrick Georgi
	It's an attempt to consolidate the access code, even if there are still multiple implementations in the code. Change-Id: I4b2b9cbc24a445f8fa4e0148f52fd15950535240 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18265 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-10	ddr3 spd: Rename read_spd_from_cbfs() to read_ddr3_spd_from_cbfs()	Patrick Georgi
	Since it checks for DDR3 style checksums, it's a more appropriate name. Also make its configuration local for a future code move. Change-Id: I417ae165579618d9215b8ca5f0500ff9a61af42f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18264 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-01-21	pcengines/apu2: Refactor reading memory strap	Kyösti Mälkki
	Change-Id: Ie4f80619d9417200a007fc65154b97a5bc05f2f8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18152 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-19	pcengines/apu2: add board support	Piotr Król
	Initial work based on db-ft3b-ls and code released by Eltan. Board boots with some limitation. Now the AGESA binary is harcoded and board specific until it's fixed by the SoC vendor. memtest86+ from external repo skips looking for SPD on SMBus, which when performed cause memtest86+ to hang. Still didn't tried whole test suit. SeaBIOS 1.9.3 have some problems with USB which lead to no booting in some cases. Full log: https://gist.github.com/pietrushnic/787cbf63f610ff4f6b4ac13e5c20b872 SeaBIOS from PC Engines repository (https://github.com/pcengines/seabios) works fine. Those changes are planned for upstream. Information about obtaining and booting Voyage Linux: https://github.com/pcengines/apu2-documentation#building-firmware-using-apu2-image-builder Change-Id: Id23e448e27f4bba47b7e9e7fa7679e2690c6e4bc Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/14138 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>