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2015-10-29pcengines/apu1: adapt comments in devicetree to boardFelix Held
Change-Id: I09d2449af9c1562f4f3d5af1e8764b82b6550007 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/12223 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-10-15pcengines/apu1: Fill serial number in SMBIOSKyösti Mälkki
Serial number is derived from the MAC address of first NIC. Change-Id: I91e5555b462cca87d48fb56c83aedd1eb02eba62 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/11901 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-10-15pcengines/apu1: Fix CRCs in SPD fileKyösti Mälkki
Do this to wipe error message and hexdump of SPD from console log. Change-Id: I45ffcb1c80aecf43b79d93faedcd62c8f0023cb7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/11900 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-15pcengines/apu1: Fix SPD for 4GB modelKyösti Mälkki
Value of tRFCmin was incorrectly using 2 Gigabit chip data. There was no observed instability or bug reports because of this. Change-Id: Ifa03b883afa5a304dd20caf3d4d0383c6cfebdb8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/11899 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-09-30pcengines/apu1: Add CMOS/NVRAM supportMaxime de Roucy
Inspired by the Sage source code (itself from coreboot). Change-Id: I4864923166efb200882d895c572d1ee060c71951 Signed-off-by: Maxime de Roucy <maxime.deroucy@gmail.com> Reviewed-on: http://review.coreboot.org/11730 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-09-30amd/family14: Add k10temp thermal zone.Tobias Diedrich
The thermal sensor interface exposed in function 3 of the northbridge is a more convenient and faster way to access the processor-internal thermal sensor than using the SMBus/SB-TSI interface from the FCH, see the Family14 BKDG: "Tctl is a processor temperature control value used for processor thermal management. Tctl is accessible through SB-TSI and D18F3xA4[CurTmp]. Tctl is a temperature on its own scale aligned to the processors cooling requirements" Also on at least some of these boards the existing thermal zone is broken and always returns 40C (the default value if the SMBus read failed) because the SMBus muxing register (SmBus0Sel) is not set up correctly. Case in point: The fallback "smbus read failed" temperature is 40 C and the the logs taken from the board status repository for the Asrock E350M1 board all show: "ACPI: Thermal Zone [TZ00] (40 C)" e.g. http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asrock/e350m1/4.0-5054-gf584218/2013-12-20T20:56:20Z/kernel_log.txt#l390 and http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asrock/e350m1/4.0-7030-g6d7de4f/2014-10-16T15:34:19Z/kernel_console.txt#l404 and http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asrock/e350m1/4.0-9989-gf2dfef0/2015-06-13T00:22:49Z/kernel_log.txt#l425 Example lm-sensors output with this patch on the pcengines APU1, on Linux 4.1.0-rc8+ (wiht both CONFIG_ACPI_THERMAL and CONFIG_SENSORS_K10TEMP enabled): acpitz-virtual-0 Adapter: Virtual device temp1: +54.0 C (crit = +100.0 C) k10temp-pci-00c3 Adapter: PCI adapter temp1: +54.0 C (high = +70.0 C) (crit = +100.0 C, hyst = +97.0 C) Change-Id: Id9c5b783ba424246816677099ec6651814e59f21 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/10940 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-22coreboot: introduce commonlibAaron Durbin
Instead of reaching into src/include and re-writing code allow for cleaner code sharing within coreboot and its utilities. The additional thing needed at this point is for the utilities to provide a printk() declaration within a <console/console.h> file. That way code which uses printk() can than be mapped properly to verbosity of utility parameters. Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11592 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-06-24pcengines/apu1: Remove unused ide.aslTobias Diedrich
The APU1 board has no IDE port, remove ide.asl. Change-Id: I76b926969748de79ac1281ed50b37e9ade1a6771 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/10622 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-23pcengines/apu1: 64bit fixesStefan Reinauer
Change-Id: Iacad070f43534a8b27a2473a6a2854bc2f6e607a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10598 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-17pcengines/apu1: Add ACPI led, button and GPIO devices.Tobias Diedrich
Provide ACPI devices with devicetree-compatible annotations for the three leds and the button of the APU1, as well as the GPIO driver. This will cause the Linux kernel to automatically load the following modules: leds_gpio (CONFIG_LEDS_GPIO) gpio_keys_polled (CONFIG_KEYBOARD_GPIO_POLLED) gpio_sb8xx (CONFIG_GPIO_SB8XX) See http://events.linuxfoundation.org/sites/events/files/slides/ACPI_vs_DT.pdf and https://lwn.net/Articles/612062/ for some more information on how the PRP0001 HID works. To make this usable a Linux GPIO driver for the AMD chipset is also required, which I am currently working on, but have not submitted upstream yet. Leds have been named after the convention in Documentation/leds/leds-class.txt: LED Device Naming ================= Is currently of the form: "devicename:colour:function" For comparison, on an OpenWRT device: GPIOs 0-21, ath79: gpio-1 (tp-link:green:usb ) out hi gpio-2 (tp-link:green:system) out lo gpio-3 (reset ) in hi gpio-5 (tp-link:green:qss ) out lo gpio-7 (qss ) in hi gpio-9 (tp-link:green:wlan ) out lo gpio-18 (rtl8366rb ) in hi gpio-19 (rtl8366rb ) in hi On the apu1: GPIOs 288-511, platform/PRP0001:00, AMD SB8XX/SB9XX/A5X/A8X GPIO driver: gpio-475 (switch1 ) in hi gpio-477 (apu1:green:led1 ) out hi gpio-478 (apu1:green:led2 ) out hi gpio-479 (apu1:green:led3 ) out hi Change-Id: I956ee92d9d98ef27a83ccb30d314543bd8634f2c Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/10540 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-14pcengines/apu1: Remove unused smbus.aslTobias Diedrich
The smbus.asl operation regions prevent the Linux i2c driver (i2c_piix4) for this chipset from claiming the ioport ranges and thus it fails to load. The methods defined in smbus.asl are not used in the DSDT and also don't exist in the DSDT of the vendor firmware. In particular due to the following check in i2c-piix4.c will fail unless acpi_enforce_resources=no is explicitly set on the Linux kernel parameters: if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) return -ENODEV; Depending on kernel options the only error message printed is ACPI Warning: SystemIO range 0x0000000000000B00-0x0000000000000B07 conflicts with OpRegion 0x0000000000000B00-0x0000000000000B0B (\SMB0) (20150410/utaddress-254) ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver However since it does not implement a standard interface there is no native ACPI driver for smbus.asl. Change-Id: Id8401e8b36f0e2412d490a92c20540a04d853125 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/10539 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-08Remove empty lines at end of fileElyes HAOUAS
Used command line to remove empty lines at end of file: find . -type f -exec sed -i -e :a -e '/^\n*$/{$d;N;};/\n$/ba' {} \; Change-Id: I816ac9666b6dbb7c7e47843672f0d5cc499766a3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/10446 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-26pcengines/apu1: Enable HAVE_ACPI_RESUMEKyösti Mälkki
Note: apu1c models do not support this. That we expose S3 in ACPI table while it is not available, is a wider issue to solve. Change-Id: I9b07550d0523593f51c1882a40cccd783115057b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10315 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-24AGESA binaryPI boards: Drop annoying commentaryKyösti Mälkki
Same comments were already removed for the latest board, the amd/lamar. Change-Id: Ie244f838409c567c11f7444c9cf17de72e49dbb0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10283 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-19pcengines/apu1: Add switch between UART and GPIO modesKyösti Mälkki
These are alternative customer options connected to J19 header. We need to avoid modifying devicetree.cb, so we fix devicetree for the super-io device-enables at runtime instead. Change-Id: I04a79974b9bdf52b09ffc1b1362e201eab1ee011 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10178 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-10AGESA: Drop unused AGESA_MEM_TABLEKyösti Mälkki
These tables are not referenced anywhere, thus all comments about adjustments are void. Also drop stub AgesaReadSpd that is all commented out. Change-Id: I12233ea0dc4baaf36a75f359c52cc59c9b6dad79 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10143 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-04-27kbuild: automatically include southbridgesStefan Reinauer
This change switches all southbridge vendors and southbridges to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in southbridge/Makefile.inc or in southbridge/<vendor>/Makefile.inc. In order to be able to drop southbridge/amd/Makefile.inc, some scattered source files had to be moved to a southbridge/amd/common directory, in accordance to what we are doing on other architectures already. This means, vendor and southbridge directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: I79bd644a0a3c4e8320c80f8cc7a7f8ffd65d32f2 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9796 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-18kconfig: automatically include mainboardsStefan Reinauer
This change switches all mainboard vendors and mainboards to be autoincluded by Kconfig, rather than having to be mentioned explicitly. This means, vendor and mainboard directories are becoming more "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree mainboards / components to be built with a given coreboot version (given that the API did not change) Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: Ib68ce1478a2e12562aeac6297128a21eb174d58a Reviewed-on: http://review.coreboot.org/9295 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-01mainboards: fix spd generationAaron Durbin
echo is evaluated by a shell builtin producing non-binary spd data of the form '-e -n \<byte>'. Correct this by using printf builtin which does the equivalent and is more cross platform friendly. Boards changed: gizmosphere/gizmo gizmosphere/gizmo2 google/bolt google/falco google/link google/peppy google/rambi google/samus google/slippy pcengines/apu1 Change-Id: Iefdaf59903b9682cc88c94fd991883b560616492 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9196 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-30Update hex values to CBFS binary name types in MakefilesMartin Roth
These binaries were being added to CBFS using hexadecimal values instead of the CBFS binary type names. The same value was being used in different places for different things. For example, the value 0xAB is used for SPDs, MRC & FSP binaries. This patch uses CBFS type names instead of hex values everywhere a hex value was previously used. Change-Id: Id5ac74c3095eb02a2b39d25104a25933304a8389 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8978 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-07AGESA: Use same HeapManager for all BiosCallOutsKyösti Mälkki
We do not allow platforms to mess around with memory layout. Change-Id: I316ff522c8833fa3b7ad20f2c5a9cae21f4174d8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8604 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-23pcengines/apu1: Fix 0:15.x PCIe root portsKyösti Mälkki
Change gpp_configuration to GPP_CFGMODE_X1111 (was X4000), this is done to only advertise x1 lane width for PCIe link 0:15.0. Hide functions of PCIe links that have no slots connected. Our PCI infrastructure does not support bridge devices that are set off in devicetree but remain visible in the PCI hardware tree. Change-Id: If90919634995076ab0f029baece3ba9cb8f3f3b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8388 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23pcengines/apu1: Fix and clean up devicetreeKyösti Mälkki
Remove functions 0:12.1 and 0:13.1 that do not exist in the hardware. Disable 0:14.1 IDE controller, as it would only be used with SATA ports 4 and 5 that are not populated with connectors in the hardware. Disable 0:14.2 HD audio, as it is not implemented in the hardware Disable 0:14.5 OHCI controller, as ports behind this USB1.1 -only controller are not populated in the hardware. Fix some alignment and whitespace. To my knowledge these changes are not included with SAGE release pcengines.apu_139_osp.tar.gz, but that tarball does not contain either devicetree.cb or a pre-compiled static.c file so I cannot tell for sure. Change-Id: Idcb8e76645fce7e89a37ff7007531b668f472131 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8328 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23pcengines/apu1: Fix PCI device 16 interruptsKyösti Mälkki
Interrupts from USB controllers 0:16.0 and 0:16.2 were not routed in PIC mode. The only affected peripheral was the SD card reader. This patch is not included with SAGE release pcengines.apu_139_osp.tar.gz. Change-Id: Ie7f0fa3751b46cca0132bd6dcada3628c6a45efb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8327 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-02-23pcengines/apu1: Implement board GPIOsKyösti Mälkki
Some GPIO pins are shared with (disabled) PCI bridge 0:14.4. As our PCI subsystem currently does not configure PCI bridges that are marked disabled, but remain visible in the hardware, we cannot mark 0:14.4 disabled in devicetree just yet. Change-Id: Ibc5d950662d633a07d62fd5a5984a56d8e5f959d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8326 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23pcengines/apu1: New board PC Engines APU1Kyösti Mälkki
While we cannot recreate exact copies of PC Engines APU1 firmware images, I shall upstream the vital changes for coreboot from the following tarballs SAGE has published to meet GPL: SageBios_PCEngines_APU_sources_for_publishing_20140405_GPL_package.tar.gz md5sum: ce5f54723e4fe3b63a1a3e35586728d4 pcengines.apu_139_osp.tar.gz md5sum: af6c8ab3b85d1a5a9fbeb41efa30a1ef The patch here adds Kconfig, Makefile.inc and devicetree.cb files to match 2014/04/05 release tarball config.h and static.c files. Change-Id: Id61270b4d484f712a5c0e780a01fc81f1550b9ad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8325 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23pcengines/apu1: Fork of amd/persimmonKyösti Mälkki
Drop persimmon customization for superio, azalia, PCI-e reset etc. Change-Id: I35f49ca67e6cc2df826f24e5a4bb3db5bb6f711e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8324 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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