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path: root/src/mainboard/pcengines/apu1/mainboard.c
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2018-05-08mb/pcengines: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I8a05bb00dc640fafa1c8e2eaac6427fdb0169f39 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-09-12AGESA CIMX: Remove empty set_pcie_(de)resetKyösti Mälkki
For boards with cimx/sb800, mainboards defined only empty stubs. Reset functionality is handled as BiosCallout. For amd/inagua, the defined function was actually initial GPIO programming. For cimx/sb700, function had prototypes but no callers. For cimx/sb900, everything was commented out already. Change-Id: I936feb4fc41d903078620c919a733bb9f39c3efb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-12AGESA boards: Clean up some includesKyösti Mälkki
Change-Id: I84c70aa04ab556a3898d3525f7b9aab85812f61d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-07AGESA: Remove leftover s3resume includeKyösti Mälkki
Change-Id: I7a1574259f73a52b66d03c686ae8ab70345c36ed Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18586 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-10-28pcengines/apu1: Add RS485 configurationKyösti Mälkki
In RS485 mode RTS line acts as a transceiver direction control. The datasheet is not very clear about the polarity but register setting here is tested to drive nRTS line high when transmitting. Also note revision of B of the super-IO has errata and 8N1 setting does not work properly, you would need revision C of the chip assembled to fix this. Change-Id: I705fe0c5a5f8369b0a9358a64c74500238b5c4ba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14998 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-06-05pcengines/apu1: Add SMBIOS SKU fieldKyösti Mälkki
Just the memory size, there is no strap to identify PCB revision. Change-Id: I65b2f5b0ac6930bead60ea0a551f13a6bcab24c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14997 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-05-30pcengines/apu1: Rename Kconfig variables for pinmuxKyösti Mälkki
Add APU1 prefix because Kconfig throws errors if we try to define the same variables as choice-entry for APU2 board. Change-Id: Ic071600dd88e391a8a278d63aad13abd01fd3c9d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14988 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-03-15pcengines/apu1: Enable USB overcurrent detection.Tobias Diedrich
The two external USB ports and the internal USB header have overcurrent protection chips with the low-active overcurrent signal connected to the chipset. The power-on default for this register disables the software detection of overcurrent conditions. After setting the register Linux correctly shows the overcurrent condition in the kernel log (tested by shorting the 5v and gnd lines on J14 / the internal USB header): [ 2015.229921] usb usb1-port3: over-current condition [ 2015.449925] usb usb1-port4: over-current condition Simlar for the external ports: [ 256.237916] usb usb1-port1: over-current condition [ 256.458084] usb usb1-port5: over-current condition Note that each signal is shared between two ports: usboc0#: External ports (port1/5) usboc1#: Internal ports (port3/4) Change-Id: I02d498053b8ec61dc206e74a96c4a1dcfd4fae92 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/14084 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-19pcengines/apu1: enable use of clkreq pinsFelix Held
only enable pcie gpp clocks when the corresponding clkreq pin is asserted Change-Id: I7822d011bb94867d470c0194e6b652833c395cb2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/12353 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-11-19pcengines/apu1: disable unused clock outputsFelix Held
disable unconnected FCH clock outputs to save some power Change-Id: Ib3efebb8656392d58d762c23827168017d273de8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/12082 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-15pcengines/apu1: Fill serial number in SMBIOSKyösti Mälkki
Serial number is derived from the MAC address of first NIC. Change-Id: I91e5555b462cca87d48fb56c83aedd1eb02eba62 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/11901 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-19pcengines/apu1: Add switch between UART and GPIO modesKyösti Mälkki
These are alternative customer options connected to J19 header. We need to avoid modifying devicetree.cb, so we fix devicetree for the super-io device-enables at runtime instead. Change-Id: I04a79974b9bdf52b09ffc1b1362e201eab1ee011 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10178 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-27kbuild: automatically include southbridgesStefan Reinauer
This change switches all southbridge vendors and southbridges to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in southbridge/Makefile.inc or in southbridge/<vendor>/Makefile.inc. In order to be able to drop southbridge/amd/Makefile.inc, some scattered source files had to be moved to a southbridge/amd/common directory, in accordance to what we are doing on other architectures already. This means, vendor and southbridge directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: I79bd644a0a3c4e8320c80f8cc7a7f8ffd65d32f2 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9796 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-02-23pcengines/apu1: Fix PCI device 16 interruptsKyösti Mälkki
Interrupts from USB controllers 0:16.0 and 0:16.2 were not routed in PIC mode. The only affected peripheral was the SD card reader. This patch is not included with SAGE release pcengines.apu_139_osp.tar.gz. Change-Id: Ie7f0fa3751b46cca0132bd6dcada3628c6a45efb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8327 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-02-23pcengines/apu1: Implement board GPIOsKyösti Mälkki
Some GPIO pins are shared with (disabled) PCI bridge 0:14.4. As our PCI subsystem currently does not configure PCI bridges that are marked disabled, but remain visible in the hardware, we cannot mark 0:14.4 disabled in devicetree just yet. Change-Id: Ibc5d950662d633a07d62fd5a5984a56d8e5f959d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8326 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23pcengines/apu1: New board PC Engines APU1Kyösti Mälkki
While we cannot recreate exact copies of PC Engines APU1 firmware images, I shall upstream the vital changes for coreboot from the following tarballs SAGE has published to meet GPL: SageBios_PCEngines_APU_sources_for_publishing_20140405_GPL_package.tar.gz md5sum: ce5f54723e4fe3b63a1a3e35586728d4 pcengines.apu_139_osp.tar.gz md5sum: af6c8ab3b85d1a5a9fbeb41efa30a1ef The patch here adds Kconfig, Makefile.inc and devicetree.cb files to match 2014/04/05 release tarball config.h and static.c files. Change-Id: Id61270b4d484f712a5c0e780a01fc81f1550b9ad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8325 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23pcengines/apu1: Fork of amd/persimmonKyösti Mälkki
Drop persimmon customization for superio, azalia, PCI-e reset etc. Change-Id: I35f49ca67e6cc2df826f24e5a4bb3db5bb6f711e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8324 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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