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path: root/src/mainboard/pcengines/apu1/devicetree.cb
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2015-02-23pcengines/apu1: Fix 0:15.x PCIe root portsKyösti Mälkki
Change gpp_configuration to GPP_CFGMODE_X1111 (was X4000), this is done to only advertise x1 lane width for PCIe link 0:15.0. Hide functions of PCIe links that have no slots connected. Our PCI infrastructure does not support bridge devices that are set off in devicetree but remain visible in the PCI hardware tree. Change-Id: If90919634995076ab0f029baece3ba9cb8f3f3b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8388 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23pcengines/apu1: Fix and clean up devicetreeKyösti Mälkki
Remove functions 0:12.1 and 0:13.1 that do not exist in the hardware. Disable 0:14.1 IDE controller, as it would only be used with SATA ports 4 and 5 that are not populated with connectors in the hardware. Disable 0:14.2 HD audio, as it is not implemented in the hardware Disable 0:14.5 OHCI controller, as ports behind this USB1.1 -only controller are not populated in the hardware. Fix some alignment and whitespace. To my knowledge these changes are not included with SAGE release pcengines.apu_139_osp.tar.gz, but that tarball does not contain either devicetree.cb or a pre-compiled static.c file so I cannot tell for sure. Change-Id: Idcb8e76645fce7e89a37ff7007531b668f472131 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8328 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23pcengines/apu1: Implement board GPIOsKyösti Mälkki
Some GPIO pins are shared with (disabled) PCI bridge 0:14.4. As our PCI subsystem currently does not configure PCI bridges that are marked disabled, but remain visible in the hardware, we cannot mark 0:14.4 disabled in devicetree just yet. Change-Id: Ibc5d950662d633a07d62fd5a5984a56d8e5f959d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8326 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23pcengines/apu1: New board PC Engines APU1Kyösti Mälkki
While we cannot recreate exact copies of PC Engines APU1 firmware images, I shall upstream the vital changes for coreboot from the following tarballs SAGE has published to meet GPL: SageBios_PCEngines_APU_sources_for_publishing_20140405_GPL_package.tar.gz md5sum: ce5f54723e4fe3b63a1a3e35586728d4 pcengines.apu_139_osp.tar.gz md5sum: af6c8ab3b85d1a5a9fbeb41efa30a1ef The patch here adds Kconfig, Makefile.inc and devicetree.cb files to match 2014/04/05 release tarball config.h and static.c files. Change-Id: Id61270b4d484f712a5c0e780a01fc81f1550b9ad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8325 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23pcengines/apu1: Fork of amd/persimmonKyösti Mälkki
Drop persimmon customization for superio, azalia, PCI-e reset etc. Change-Id: I35f49ca67e6cc2df826f24e5a4bb3db5bb6f711e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8324 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>