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Update UPD IIO bifurcation at run-time according to different Riser
cards. For detail please reference
Facebook Server Intel Motherboard v4.0, Sec. 10.1.2 Riser card types.
With the engineering build FSP, it can only configure IIO for
one socket so my local test needs to remove all socket1 elements
from tp_iio_bifur_table.
This change relies on [1] and need to add GPP_C15 and GPP_C16 to
early_gpio_table for gpio configuration in bootblock.
[1] https://review.coreboot.org/c/coreboot/+/39427/
Tested=OCP Tioga Pass can see socket0 IIO being updated with
an engineering build FSP.
Change-Id: I8e63a233a2235cd45b14b20542e6efab3de17899
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
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Enable aspeed's function that port 80h direct to GPIO for LED display,
refer to section 9.4 Port 80h Direct to GPIO Guide of aspeed's
Application Design Guide, also configure GPIO to UART for output
serial console messages.
Tested=Check if port 80h LED debug card can display POST codes at
early stage, and serial console can see the related messages.
Change-Id: I087d5a81b881533b4550c193e4e9720a134fb8e7
Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40481
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tioga Pass platform use GPIO pin of GPP_B20 for POST complete,
BIOS needs to configure this pin for BMC to poll,
so it knows when to start to access other components.
Tested=Read GPIO status (GPIOAA7) in OpenBMC, the value is 0,
the command and result are shown as below,
root@bmc-oob:~# cat /tmp/gpionames/FM_BIOS_POST_CMPLT_N/value
0
root@bmc-oob:~#
Change-Id: I134f80153461c5acd872587038a2207586b658dd
Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: I8930e96e5f2c45b8658dc4dfe1ab57d573e7b26f
Fixes: b75bcc978a ("mb/ocp/tiogapass: Properly configure early serial output")
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I136e19fbba22b71676a0163a88ae341356c31271
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40088
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tioga Pass comes with AST2500 BMC which offers SuperIO functionality.
However we currently do not configure/enable SuperIO chip. As a result
system boots pretty silently on cold boot. Then FSP configures SuperIO
and resets the system so on next boot serial console does work. This
makes debugging difficult because pre-FSP output is invisible.
This patch enables bootblock to properly configure desired BMC SuperIO
port so early serial output is visible.
TEST=do a cold boot on OCP Tioga Pass, observe bootblock output starting
from bootblock.
Change-Id: Iff8e6a862858d733f529bb9b8c65e22e5ec6b521
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
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Refactor the code and split it into Xeon common and CPU-specific code.
Move most Skylake-SP code into skx/ and keep common code in the current
folder.
This is a preparation for future work that will enable next
generation server CPU.
TEST=Tested on OCP Tioga Pass. There does not seem to be degradation
of stability as far as I could tell.
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39601
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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A bigger than zero value of bmc_boot_timeout must be set
for KCS ipmi_get_bmc_self_test_result() to run, otherwise
the self test result will be error and won't write SMBIOS
type 38 table. Here we set 60 seconds as the maximal self
test timeout.
Tested=Check if the BMC IPMI response data and SMBIOS type
38 on OCP Tioga Pass are correct or not.
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: I3678973736a675ed22b5bc9da20a2ca947220f4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I426518e8e18de1c8efcfb7ecb0835df3e257dca1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39608
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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If we don't pretend to have binaries, there is no need to add fake ones.
This also fixes building the default config.
Change-Id: I8f933f24a734a9ce3d82ef57f7f234ee4dfa86e9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39383
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH. Skylake-SP is a processor in Intel Xeon
Scalable Processor family.
Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR
This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.
Towards successful gerrit buildbot build, note that:
* microcode is in coreboot intel-microcode submodule repo.
* IFD binary is included in this patch.
* Dummy ME binary is used, as it may take long time for Intel
ME binary to be available in public domain.
* Fake FSP binary is used, as at this moment the SKX-SP
FSP binary is not going to be available in public domain.
Known issues (Not intend to address in this initial support for
Xeon-SP processors):
* c6 state is not supported.
* dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
* SMM handlers are not added.
Following are some command execution with CentOS booted from
local SATA disk:
[root@localhost ~]# lscpu
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 72
On-line CPU(s) list: 0-71
Thread(s) per core: 2
Core(s) per socket: 18
Socket(s): 2
NUMA node(s): 2
Vendor ID: GenuineIntel
CPU family: 6
Model: 85
Model name: Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz
Stepping: 4
CPU MHz: 140.415
BogoMIPS: 4626.46
Virtualization: VT-x
L1d cache: 32K
L1i cache: 32K
L2 cache: 1024K
L3 cache: 25344K
NUMA node0 CPU(s): 0-17,36-53
NUMA node1 CPU(s): 18-35,54-71
[root@localhost ~]# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500
inet 172.23.68.190 netmask 255.255.0.0 broadcast 172.23.255.255
inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0 prefixlen 64 //cut
inet6 fe80::268a:7ff:fe57:5af0 prefixlen 64 scopeid 0x20<link>
inet6 2620:10d:c082:9063::5d2 prefixlen 128 scopeid 0x0<global>
ether 24:8a:07:57:5a:f0 txqueuelen 1000 (Ethernet)
RX packets 84249 bytes 6371591 (6.0 MiB)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 8418 bytes 748781 (731.2 KiB)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
lo: flags=73<UP,LOOPBACK,RUNNING> mtu 65536
inet 127.0.0.1 netmask 255.0.0.0
inet6 ::1 prefixlen 128 scopeid 0x10<host>
loop txqueuelen 1000 (Local Loopback)
RX packets 613 bytes 63906 (62.4 KiB)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 613 bytes 63906 (62.4 KiB)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
[root@localhost ~]# cbmem
36 entries total:
// Lines were cut to avoid checkpatch.pl warnings
Total Time: 96,243,882,140,175,829
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Tested-by: johnny_lin@wiwynn.com
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: I3d9b6bb48bfd15c0182448f774e9af1e0c944fd5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Add VPD variables for enabling/disabling FRB2 watchdog timer and
setting the timer countdown value. By default it would start the
timer and trigger hard reset when it's expired. The timer is
expected to be stopped later by payload or OS.
Right now the timer is started after FSP-M. Ideally it should be
before FSP-M (to detect memory training error).
Tested on OCP Mono Lake.
Change-Id: I82b244d08380a0461c92662e025d8b95b3133e23
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Add a GPIO table for Monolake to initialize GPIOs with custom board
configurations.
Tested on Monolake.
Change-Id: I74906bf9395a333be6250ffbd181da536e016f30
Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Disable root port IOU0 to which built-in NIC is attached.
TEST=on OCP monolake, hide built-in NIC and make sure OS does not report
built-in NIC
Change-Id: I2384e7dd073355f0ced2902ac2d8418996b1c5aa
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Change-Id: I28a21d64e2781af294670a94c1fc88fb81e80f9e
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35492
Reviewed-by: Andrey Petrov <anpetrov@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Implement Locator and Bank fields (as reported by dmidecode) to match
vendor BIOS.
TEST=on OCP monolake, run dmidecode tool and see that "Locator" field
matches expectation.
Change-Id: Ia271ff1e596ba469cf42e23d8390401c27670a27
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Summary:
This patch calls monolake board specific function to query
settings stored in VPD binary blob to configure FSP UPD
variable HyperThreading.
Test Plan:
* Build an OCP MonoLake coreboot image, run following command
to initialize RW_VPD and insert HyperThreading key:
vpd -f build/coreboot.rom -O -i RW_VPD -s 'HyperThreading=0'
* Flash the image to MonoLake, boot and observe following
message in boot log:
Detected 16 CPU threads
If RW_VPD partition does not exist, or if HyperThreading
key/value pair does not exist, the boot log has:
Detected 32 CPU threads
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I799d27734fe4b67cd1f40cae710151a01562b1b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Remove duplicated code and instead use the IPMI KCS driver, which provides
the same functionality.
Change-Id: I419713c9bef02084cca1ff4cf11c33c2e3e8d3c1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <anpetrov@fb.com>
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coreboot would clear CMOS by request via IPMI command, for example
BMC can issue "bios-util server --boot_order enable --clear_CMOS"
to set the request and reboot the system, then coreboot would clear CMOS
on the next boot.
Tested on Mono Lake
Change-Id: I21d44557896680cfac3c3b6d83e07b755b242cad
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34857
Reviewed-by: Johnny Lin
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I240e9e767c9b38b3b06d3978fd20ddb37a96e470
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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* Enable decoding the IPMI KCS to LPC
* Select the IPMI driver
* Add the PNP device that holds the IPMI KCS base address
Tested on Wedge100s.
Change-Id: I35634bbcbe6893bd72ec7e41f6ca7bba09d819a2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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That's how we do it these days.
Change-Id: I6bf6460440d0f2e6973734ba8894a4be981d03c5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32812
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Changes includes:
- enable TPM1 + add entry in devicetree
- configure LPC IO to make IPMI work + add entry in devicetree
- introduce DSDT and SMBIOS entries for IPMI to make it detectable
by ipmi_si driver
Signed-off-by: Lukasz Siudut <lsiudut@fb.com>
Change-Id: Ia975643064075f1f861f4ead6f24ed71f345ea04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Change-Id: I6095c3b30990b530c5bc4e2c808879252680e1d7
Signed-off-by: Andrea Barberio <barberio@fb.com>
Signed-off-by: David Hendricks <dhendrix@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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For Chrome OS (or vboot), The PRESERVE flags should be applied on
following sections:
RO_PRESERVE, RO_VPD, RW_PRESERVE, RW_ELOG, RW_NVRAM, RW_SMMSTORE,
RW_VPD, RO_FSG (b:116326638), SI_GBE (chromium:936768),
SI_PDR (chromium:936768)
With the new PRESERVE flag, we don't need RO_PRESERVE and RW_PRESERVE in
the future. But it's still no harm to use it if there are multiple
sections all needing to be preserved.
BUG=chromium:936768
TEST=Builds google/eve and google/kukui inside Chrome OS source tree.
Also boots successfully on eve and kukui devices.
Change-Id: I6664ae3d955001ed14374e2788d400ba5fb9b7f8
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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PCI config accessors are no longer indirectly included
from <arch/io.h> use <device/pci_ops.h> instead.
Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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We experienced booting issues during FSP-M phase. Applying fix that was
introduced for wedge100s - 817994c1bec (mb/ocp/wedge100s/romstage:
Workaround broken platform state) - helped and systems started to
boot properly.
Signed-off-by: Lukasz Siudut <lsiudut@fb.com>
Change-Id: Ibfbe9d19c7413098c56d1b6131640097fdf731ab
Reviewed-on: https://review.coreboot.org/c/31435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Match devicetree what's present and in use.
Tested on wedge100s:
All PCI devices show up.
Change-Id: I669d059da1876ed669793db8c7eb1b96b481cb4c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/31228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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It has 2x 10GbE XGMII and 1x i210IT on PCIe, but no GBE.
Change-Id: I641c336350a0b05f3db7603cc7f6281ff3b0c388
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/31198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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need it
Hide "Add gigabit ethernet firmware" option for boards that do not
use GbE firmware in GbE section.
The option is now hidden by default and can be reenabled on a
per-board basis by selecting MAINBOARD_USES_IFD_GBE_REGION in the
mainboards Kconfig.
The following boards seem to use this:
mb/roda/rv11
mb/ocp/wedge100s
mb/ocp/monolake
mb/lenovo/x230
mb/lenovo/x220
mb/lenovo/x201
mb/lenovo/x200
mb/lenovo/t530
mb/lenovo/t520
mb/lenovo/t430s
mb/lenovo/t430
mb/lenovo/t420s
mb/lenovo/t420
mb/lenovo/t400
mb/kontron/ktqm77
mb/intel/saddlebrook
mb/intel/kblrvp
mb/intel/dg43gt
mb/intel/dcp847ske
mb/intel/coffeelake_rvp
mb/intel/camelbackmountain_fsp
mb/hp/revolve_810_g1
mb/hp/folio_9470m
mb/hp/compaq_8200_elite_sff
mb/hp/8770w
mb/hp/8470p
mb/hp/8460p
mb/hp/2760p
mb/hp/2570p
mb/google/sarien
mb/facebook/watson
mb/compulab/intense_pc
mb/asus/maximus_iv_gene-z
The boards were identified by looking at devicetree.cb, but this
list is possibly still incomplete.
Change-Id: Ibfb07902ad93fe5ff2bd4f869abcf6579f7b5a79
Signed-off-by: Jan Tatje <jan@jnt.io>
Reviewed-on: https://review.coreboot.org/c/30790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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* Enable COM1, COM2, PMC1 and PMC2
TODO: Look at additional configuration and EC space.
Tested on wedge100s. The serial works without CONFIG_CONSOLE_SERIAL.
Change-Id: Id139bf243c7e7ac3e51a0ddb19d2396452341e29
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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* Route IO 0x6e/0x6f to LPC bus
* Setup ITE8526 in early_mainboard_romstage_entry
* Fix romstage serial console by disabling internal uart default setting
* Unselect CONFIG_INTEGRATED_UART, as it doesn't use internal UARTs
* Select CONFIG_DRIVERS_UART_8250IO, as it has a SuperIO serial
* Configure UPDs related to serial
Change-Id: I59cd83ed43dbf4ee26685e4a573de153291f7074
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Move early_mainboard_romstage_entry before console_init.
Allows to setup a SuperIO, if any, for serial console.
Change-Id: I370263a6197a4c0c805352f07fedddbee1b8e247
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This allows to set up the SuperIO in the C_ENVIRONMENT_BOOTBLOCK
bootblocks. It is likely unnecessary to do this in verstage.
This also renames COMMON_ROMSTAGE to COMMON_PRE_RAM.
Change-Id: I3d999611baa1e79c79fe6b1f01822ebaa5f85daf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Sometimes the platform boots in an invalid state, that will cause
FSP-M to fail. As a board_reset() doesn't fix it, issue an full_reset()
as soon as the IA32_FEATURE_CONTROL MSR is locked at beging of romstage.
Tested on wedge100s. After full reset the system behaves as normal.
Change-Id: I1a382b8fb650311b0c24b48e0986d22edfa2d261
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Field 'OEMID' & "OEM Table ID" are related to DSDT table
not to mainboard.
So use macro to set them respectvely to "COREv4" and
"COREBOOT".
Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
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* Add RO only FMAP.
* Add kconfig options.
Tested=OCP Wedge100s
Change-Id: I1979e0263e41f21c01c407ac81ad1198a53741e8
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version.
This will cause the AML interpreter to use 32-bit integers and math
if the version is 1, and 64-bit if the version is >=2.
Current spec version is 2 for ACPI 6.2-a.
Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29626
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The assignment of header->checksum was in some cases done twice, or
unnecessarily split into two lines.
Change-Id: Ib0c0890d7589e6a24b11e9bda10e6969c7d73c56
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Change-Id: Id7e8ad63de2a6094c66cbd47ae9b7707a9af4e81
Signed-off-by: Mikolaj Walczak <mwalczak@fb.com>
Reviewed-on: https://review.coreboot.org/28529
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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this enables spi console for wedge100s with broadwell_de. the console
size is 64kb. enabling spi console in `board.fmd` enables code which
calls into `timer_monotonic_get` (from `spi_flash_cmd_poll_bit`) and
`udelay` (from `ich_status_poll`). this patch selects `TSC_CONSTANT_RATE`
in fsp_broadwell_de's Kconfig to satisfy that.
Change-Id: Ib925c5aee88b65c46a81534405c364dd5649f8e8
Signed-off-by: Okash Khawaja <okash.khawaja@gmail.com>
Reviewed-on: https://review.coreboot.org/28528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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this enables mrc cache in fmap for wedge100s and always enable it in
Kconfig.
Change-Id: I27cd236f67a6500b40fc3eb731397d408402f041
Signed-off-by: Okash Khawaja <okash.khawaja@gmail.com>
Reviewed-on: https://review.coreboot.org/28527
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I3108193c0e0b644cecb74ae0c7a7b54e24a75b58
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Use of device_t has been abandoned in ramstage.
Change-Id: I07e00afbbd2c19cf3ea6e08f228eb39e45f1ad0c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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As far as I can see this Kconfig option was used wrong ever since it
was added. According to the commit message of 107f72e (Re-declare
CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR), it was only necessary
to prevent overlapping with CAR.
Let's handle the potential overlap in C macros instead and get rid
of that option. Currently, it was only used by most FSP1.0 boards,
and only because the `fsp1_0/Kconfig` set it to CBFS_SIZE (WTF?).
Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch does the following:
1. Copy src/mainboard/intel/camelbackmountain_fsp to
src/mainboard/ocp/wedge100s.
2. Update Kconfig files
3. Add board.fmd
4. Enable VPD
The OCP Wedge100S is a 100GbE top-of-rack switch with a Xeon D-1500
com-express module. More info is available at
http://www.opencompute.org/wiki/Networking/SpecsAndDesigns.
Signed-off-by: Sudhakar Mamillapalli <sudhakar@fb.com>
Signed-off-by: David Hendricks <dhendricks@fb.com>
Change-Id: Ia150b066124953c7c0abe8ea5a13e4131194ea00
Reviewed-on: https://review.coreboot.org/25671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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This patch does the following:
1. Copies mainboard/intel/camelback_fsp to mainboard/ocp/monolake
2. Adds Kconfig files to mainboard/ocp
3. Makes minor board-specific changes (board_info.txt, Kconfig
variables)
The OCP Mono Lake platform consists of up to 4 single-socket Xeon
D-1500 microservers in a Yosemite v1 chassis. More info is available
at http://www.opencompute.org/wiki/Server/SpecsAndDesigns.
Signed-off-by: David Hendricks <dhendricks@fb.com>
Change-Id: If358162abe67e9411fd2514d48f3b3411da15f68
Reviewed-on: https://review.coreboot.org/25669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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