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2021-03-01mb/ocp/deltalake: Fill ECC type in romstageAngel Pons
Fill the ECC type in `struct memory_info` in romstage, and in SoC code. The SMBIOS override is unnecessary, and this is not mainboard-specific. Change-Id: I8370b3ee7d75914b895946b53923598adf87b522 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50179 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16mb/ocp/deltalake: Remove unused <string.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<' Change-Id: I0d2c362ba9b494bf4cce280192ec0b91dce3e8bb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-02-14ACPI: Move common _PIC methodKyösti Mälkki
Change-Id: I659835354570fb1d4860fcbddf2a51831170a374 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-04src: Remove unused <bootstate.h>Elyes HAOUAS
Change-Id: I0d2ab4144970184f46e1d0e7a2464e94fa38aa63 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-02-01drivers/security/cbnt: Fix bootblock sizeArthur Heymans
Change-Id: Ic5ad9d29f247b6f828501bfacc27a8af08761d55 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-01ipmi/ocp: Move common OCP/Facebook IPMI OEM codes into drivers/ipmi/ocpJohnny Lin
1. These are common OCP/Facebook IPMI OEM commands, move from mainboard into drivers/ipmi/ocp to avoid code duplication and provide better reusability. 2. OCP Tioga Pass enables IPMI_OCP driver. Tested=On OCP Delta Lake and Tioga Pass verify the commands still work correctly. Change-Id: Idd116a89239273fd5cc7b06c7768146085a3ed69 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2021-01-27ACPI: Add top-level ASLKyösti Mälkki
Objects that are created with acpigen need to be declared with External () for the generation of dsdt.asl to pass iasl without errors. There are some objects that are common to all platforms, and some that should be declared only conditionally. Having a top-level ASL helps to achieve this. Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-26mb/ocp/deltalake: Replace space with underscore in Locator stringJohnny Lin
Per Facebook BIOS requirements 'Locator' field should not have any space between words. Tested=On OCP Delta Lake, dmidecode -t 17 to verify. Change-Id: I2f6f1b2590c55d6da4ca32aef2f50eb332f441dc Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-26ocp/deltalake: Set C-State configMarc Jones
Set the supported C-State to C1 and C6. This matches the states in CPUID(5). Change-Id: If32b8256097b5b2bee7fb074fab105e4b54d14b3 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49803 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-19intel/xeon_sp, mb/ocp/deltalake: Rework get_stack_busnos()Maxim Polyakov
- Return the busno based on the stack number. - Replace pci_mmio_read_config32 with pci_io_read_config32 to get the register value before mapping the MMIOCFG space. - Remove the plural `s` as the function now provides one bus number. Change-Id: I6e78e31b8ab89b1bdcfdeffae2e193e698385186 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-19mb/ocp/deltalake: Make use of vpd_get_int to clean up codeJohnny Lin
Tested=On OCP Delta Lake, verify the VPD values can be read correctly. Change-Id: I1c27cb61cd52902c92b3733e53bc8e6fd6a5fe7f Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-18mb/ocp/tiogapass/ramstage.c: Remove duplicated includeElyes HAOUAS
Change-Id: I6549ad6704c62b968ff9eb59cc698107c0120fb8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-01-10soc/intel: Replace acpi_init_gnvs()Kyösti Mälkki
Rename these to soc_fill_gnvs() and move the callsite away from mb/. Change-Id: I760c36f65c6122103f2be98fc11ee13832c2772e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48716 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10mb/x/acpi_tables: Rename to mainboard_fill_gnvs()Kyösti Mälkki
Rename acpi_create_gnvs() functions under mb/ to reflect their changed functionality. Remove now empty mb/acpi_tables.c files. Change-Id: Ia366867ef73d1ade9805dc29b8e14b3073f44f60 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48707 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-30mb/ocp/deltalake: replace "POST complete" mb code with driver functionalityMichael Niewöhner
Replace the mainboard-specific code for "POST complete" signalling with devicetree entries for using the newly introduced IPMI driver functionality. Test: Boot the machine via the BMC web interface and check that sensors get read correctly by the IPMI firmware when the payload starts. Tested successfully. Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com> Change-Id: I3441c2a971cfb564b34b3a419beceb949fe295b1 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-28soc/intel/xeon_sp: Lock down IIO DFX Global registersArthur Heymans
This is required for CbNT. Change-Id: I565a95cd2e76cb1c648884be6d1954288f6e4804 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-16mb/ocp/tiogapass/devicetree.cb: Add P2SB deviceArthur Heymans
This fixes ocp/tiagopass not booting as after FSP-S the P2SB is accessed to read out or reconfigure the HPET and PCH IOAPIC BDF. Change-Id: Ia37bd0f14627980345cd07f20e935a10d4760b69 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48654 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11mb/ocp/deltalake: Update GPIO configurations according to schematicsJingle Hsu
On Delta Lake DVT, dump GPIO settings from UEFI firmware for new PCH (C621A) by util/inteltool and generate the header file by util/intelp2m. The DVT and EVT GPIO configurations are the same. The initial value of GPP_B20 (POST complete) should be high, otherwise BIC would get incorrect sensor readings and see events like PCH prochot. Tested=On OCP Delta Lake DVT, dump GPIO configurations by Intel ITP and verify the results match with the header file. Change-Id: Ic9837a22bc231a4cb919de316ff6f6ee88411ab8 Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47229 Reviewed-by: Tim Chu <Tim.Chu@quantatw.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10soc/intel/xeon_sp/nvs: Use common global NVSMarc Jones
The xeon_sp ACPI NVS and ramstage NVS were out of sync. Since there isn't anything uncommon with the soc NVS, use the Intel common NVS. This covers the NVS cases of common code used by xeon_sp. Update the mainboards for this change. Change-Id: Icf422f5b75a1ca7a3d8f3d63638b8d86a56fdd7b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2020-12-01mb/ocp/deltalake: Update SMBIOS type 8 informationTim Chu
Update port connector information for Delta Lake. Tested=Execute "dmidecode -t 8" to check all the information of SMBIOS type 8 is correct. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I880bb9a5a41077172423f78b56c19aadd93e001f Reviewed-on: https://review.coreboot.org/c/coreboot/+/47893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-25mb/ocp/deltalake: Define SMBIOS type 16 error correction type byTim Chu
RasModesEnabled Use RasModesEnabled from SystemMemoryMapHob to define SMBIOS type 16 error correction type Tested=Execute "dmidecode -t 16" to check if error correction type is correct. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I3636fcc4a874261cf484c10e2db15015ac5d7e68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-11-22mb/ocp/deltalake: Override SMBIOS type 4 cpu voltageTim Chu
Override SMBIOS type 4 cpu voltage. For Delta Lake, 1.6V is expected. Tested=Execute "dmidecode -t 4" to check if cpu voltage is correct. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I0ecbec8fb3dc79b8c3f3581d6193aade01bcd68e Reviewed-on: https://review.coreboot.org/c/coreboot/+/47562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-11-07mainboard/ocp/tiogapass: Add xeon_sp pch.aslMarc Jones
Use the xeon_sp pch.asl to include the intel common lpc.asl. Change-Id: I22ee9d325888808a9c775ecee0591b661e2bba4e Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Javier Galindo <javiergalindo@sysproconsulting.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-07mainboard/ocp/deltalake: Use xeon_sp pch.aslMarc Jones
Use the xeon_sp pch.asl to pickup the common block lpc.asl. This allows deltalake to pick up any general pch asl updates. Currently, generates the same asl. Change-Id: I5005032b030d288fdf5ca2f99d21fe8e6c752037 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47304 Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-07mainboard/ocp/tiogapass: Set longer BMC timeoutMarc Jones
The BMC isn't always ready in 60 seconds if it printing debug output. Give it 90 seconds to finish before timing out in coreboot. Change-Id: I3932d3e8fad067e8971e82b45b499801fc78079f Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Javier Galindo <javiergalindo@sysproconsulting.com>
2020-11-07vc/intel/FSP2_0/CPX-SP: update to ww45 release and add watermark optionJonathan Zhang
Intel CPX-SP FSP ww45 release annotates default values for FSP-M UPD variables. FSPM MemRefreshWatermark option support is present in FB's CPX-SP FSP binary, but not in Intel's CPX-SP FSP binary. In FB's CPX-SP FSP binary, this option takes the space of UnusedUpdSpace0[0]. For DeltaLake mainboard, if corresponding VPD variable is set, use it to control the behavior. Such control is effective when FB's CPX-SP FSP binary is used. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I57ad01f33b92bf61a6a2725dd1cdbbc99c02405d Reviewed-on: https://review.coreboot.org/c/coreboot/+/46640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-11-04mb/ocp/deltalake: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated build/dsdt.dsl files are same. Change-Id: I5bd8fe629fb969ec14dd400b6463ee1592d6903b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46207 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04mb/ocp/tiogapass: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated build/dsdt.dsl files are identical. Change-Id: Iffd6954dcb3f9fb8bcd89854d84f6944cb520dd1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46208 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-28mb/ocp/tiogapass/dsdt: Remove unnecessary commentsMaxim Polyakov
Change-Id: I6a16e2f829219f2eba8acd3ae7f371238c0d8de1 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-10-28mb/ocp/tiogapass/acpi: Exclude uncore.asl from _SB scopeMaxim Polyakov
The corresponding devices and objects are already included in the System Bus ACPI scope inside uncore.asl. There is no need to do this again in the DSDT of the motherboard. Change-Id: I98a8d60b585e2eafd76948baea0f249a029bae09 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-28mb/ocp/deltalake: Rename motherboard_fill_fadt()Jingle Hsu
Rename motherboard_fill_fadt() to the common override mainboard_fill_fadt() function to override FADT. Tested=On OCP Delta Lake, verify FADT PM Profile is set to Enterprise Server. Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com> Change-Id: Ie9ea7cc6e712d0aca57bbeac1a4154921d123be4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26mb/ocp/deltalake: Override coreboot log level via VPDJohnny Lin
Tested=On OCP Delta Lake, log level can be changed via VPD. Change-Id: I36d4b01b6fb6acc726749641df089cb3f9a4dc3e Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-10-26mb/ocp/deltalake: Use BMC version to represent ec versionTim Chu
In deltalake, there's no embedded controller and BMC version is used to represent ec version. TEST=Build with CB:45138 and CB:46070 Execute "dmidecode -t 0" to check if the firmware version is correct Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I388efd749170f0ebbb4dd4d32199675d92cc018e Reviewed-on: https://review.coreboot.org/c/coreboot/+/46071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-13{src/mb,util/autoport}: Use macro for DSDT revisionElyes HAOUAS
Change-Id: I5a5f4e7067948c5cc7a715a08f7a5a3e9b391191 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-10-13mb/ocp/deltalake: Update SMBIOS type 9 informationJingle Hsu
Update Slot Designation strings and add SSD0_M2_Boot_Drive for config A. TEST="dmidecode -t 9" to verify the results are expected. Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com> Change-Id: I3fc03a14ff7dc43d6ddf5aa36710c99dbc648afa Reviewed-on: https://review.coreboot.org/c/coreboot/+/46125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-12mb/ocp/deltalake: Select correct uart for consolePatrick Rudolph
Tested on OCP deltalake. The console now shows up on the serial. Change-Id: If4c412c1ca749f1feba47b2ce0beb52d0111be86 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-10-08mb/ocp/deltalake: Override smbios_fill_dimm_locator for type 17Johnny Lin
Override smbios_fill_dimm_locator for type 17 Locator and Bank Locator. Also remove CONFIG(GENERATE_SMBIOS_TABLES) compile option because SMBIOS is always enabled and it makes the code cleaner. One sample type 17 table displayed as below: Handle 0x0010, DMI type 17, 40 bytes Memory Device ... Locator: DIMM F0 Bank Locator: _Node0_Channel5_Dimm0 Tested=On OCP Delta Lake, the Locator and Bank Locator strings are expected. Change-Id: I84531f9ee8bc76d9529aa983bc13e64f40c93138 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-03soc/intel/xeon_sp: Use common ASL code for xeon_spMarc Jones
Move and use the common xeon_sp/cpx/acpi asl for skx/. There were only minor whitespace differences between the directories. Update the mainboards to build the moved files. TiogaPass coreboot.rom checked with BUILD_TIMELESS. Change-Id: I5058a3fe8d96075a266fb92f10707bb94308c85b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45217 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28mb/ocp/deltalake: add LPC device entry in ACPIJonathan Zhang
PCH LPC device is on CSTACK. Add LPC ACPI device entry. Without this change, following error message shows up in target OS boot log: ACPI BIOS Error (bug): Failure looking up [\_SB.PCI0.LPCB], AE_NOT_FOUND (20180105/dswload-211) ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20180105/psobject-252) ACPI Error: AE_NOT_FOUND, (SSDT:COREBOOT) while loading table (20180105/tbxfload-228) ACPI Error: 1 table load failures, 1 successful (20180105/tbxfload-246) Also TPM device is not created. TESTED=Booted DeltaLake DVT, run following command in target OS: [root@dhcp-100-96-192-153 ~]# dmesg | grep tpm [ 7.331890] tpm_tis MSFT0101:00: 2.0 TPM (device-id 0x1B, rev-id 16) Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I8614f6951389bd5c8f8f33522d0a9a9160ac3f66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-09-14src/mainboard: Remove unused include <device/pnp_ops.h>Elyes HAOUAS
Change-Id: I278fb20aa176bb09f1ff135fdfd732f0096d3808 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-14mb/ocp/deltalake: Drop redundant `select FSP_CAR`Angel Pons
This is selected by Xeon SP Kconfig already. Change-Id: If1ef7f86b27d7be74912c9ad1f9c1efbda6233e5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-09-12mb/ocp/deltalake: Enable TPM2Christian Walter
Change-Id: I6eaaf80dd2bd69096574ab967ec0c6738b05903b Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08mb/ocp/deltalake: Add SMBIOS OEM string for SPD register vendor IDJohnny Lin
Tested=On OCP Delta Lake, with FSP WW36 dmidecode -t 11 can see the SPD register vendor ID String 7: b300 0000 b300 0000 b300 0000 b300 0000 b300 0000 b300 0000 Change-Id: I15ab9b4c709eb97a03d6e08fe0bcdcb7f8607db0 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-28mb/ocp/deltalake: Configure FSP DCI via VPDJohnny Lin
Tested on OCP Delta Lake, with FSP WW34 DCI can be connected if enabled. Change-Id: I8e0dff921cef02dfc66467a2b8fa3e196fb36ac2 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-20src/mainboard: Escape variable expansion in KconfigPatrick Georgi
Kconfig 5.8 interprets $(...) itself using environment variables, which generally means that they expand to the empty string. \$(...) works with both our current and new Kconfig with the desired behavior (to pass it through unmodified). Change-Id: I726567eeb61d2035560152677d2b4548c1472be9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44584 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-14mb/ocp/deltalake: enable VT-dJonathan Zhang
Update devicetree.cb to configure VT-d to be enabled. TESTED=booted on DeltaLake config A server, and verify DMAR table. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I7d76cd9d50d3e69a4919de281f11d30851bffa3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/44281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-08-14soc/intel/xeon_sp/cpx: remove unsupported configsJonathan Zhang
coherency_support and ats_support are not supported by CPX-SP FSP. Remove them from soc_intel_xeon_sp_cpx_config struct. Remove corresponding settings from DeltaLake devicetree.cb. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ibe1c4e88817fc4be7915e95fa829f0a4c0d947f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-08-14mb/ocp/deltalake: Select CONSOLE_POSTJohnny Lin
Tested=On OCP Delta Lake, BMC SOL can see POST codes Change-Id: I2c27055475e6dadcd4282cd1bf191a1b83150f02 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-11vendorcode/intel/fsp/fsp2_0/CPX-SP: remove non-existing PSTACKsJonathan Zhang
CPX-SP has a CSTACK and 3 PSTACKs. Clean up the HOB header file to remove reference to non-existing PSTACKs. Adjust mainboard code accordingly. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ic52b01cd89fb5b3fce64686d91f017f405566acd Reviewed-on: https://review.coreboot.org/c/coreboot/+/44279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-31mb/ocp/deltalake: configure DIMM_MAXJonathan Zhang
DeltaLake is a single socket server. Its platform design has 1 DIMM slot per channel. There are 6 DIMM slots. Configure DIMM_MAX to overwrite SOC default. Change-Id: I47ecc81452fe59ed59fd3a239ffe329cbc031d7a Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44048 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-31drivers/ipmi/ocp: Add function to support OCP specific ipmi commandTim Chu
Add driver for OCP specific ipmi commands. With this driver, OCP specific ipmi command can be used after implementing functions here. TEST=Build with CB:42242 on Delta Lake, select Kconfig option: IPMI_OCP and add device in devicetree to open this function. Use ipmi-util in OpenBMC to dump raw data and check if this function work. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I2efa85978ec4ad3d75f2bd93b4139ef8059127ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/43996 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-31mb/ocp/deltalake: Update SMBIOS type 4 -- Processor InformationMorgan Jang
TEST=Execute "dmidecode -t 4" to check if the processor information is correct for Deltalake platform Change-Id: I5d075bb297f2e71a2545ab6ad82304a825ed7d19 Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-30mb/ocp/tiogapass: Add SMBIOS type8 data tableBryantOu
According to MP MB to port SMBIOS type8 data. Tested=Use "dmidecode -t 8" to dump SMBIOS data, and check if type8 tables are implemented. Change-Id: I356e645774d78c623c1398c8b1473562e1529cf2 Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-30mb/ocp/deltalake: Add VPD variable for FRB2 timer actionJohnny Lin
Tested on OCP Delta Lake, the timer action can be set correctly. Change-Id: I1013169e12455e01214d089c9398c78143af4df8 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44019 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29mb/ocp/tiogapass: Configure IPMI FRB2 watchdog timer via VPD variablesJohnny Lin
Add VPD variables for enabling/disabling FRB2 watchdog timer and setting the timer countdown value in romstage. By default it would start the timer and trigger hard reset when it's expired. The timer is expected to be stopped later by payload or OS. Add RO_VPD and RW_VPD sections. Tested on OCP Tioga Pass. Change-Id: I53b69c3c5d22c022130fd812ef26097898d913d0 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-28mb/ocp/deltalake: use common driver to configure GPIOBryant Ou
Use the common driver to configure the GPIOs on the Delta Lake platform as done for Tioga Pass in commit 89d2aa0. The GPIO settings are dumped by inteltool with original UEFI firmware, then use intelp2m to generate header file. TEST=Dump GPIO settings by Intel ITP and check if match gpio.h. Change-Id: I8005d4caa2d87b6831099bfec3a40246224f3cb5 Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26mb/ocp/tiogapass/gpio: undo set trig and bufdis for NF padsMaxim Polyakov
According to the documentation [1], RX Level/Edge Configuration (trig) and GPIO Tx/Rx Buffer Disable (bufdis) [2] settings are not applicable in native mode and BIOS does not need to configure them. Therefore, there is no need to configure this in gpio.h using PAD_CFG_NF_BUF_TRIG macros. Use PAD_CFG_NF instead and set these fields to 0. [1] Intel document #549921 [2] Intel document #336067-007US This is part of the patch set "src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ": CB:43455 - cedarisland: undo set trig and bufdis for NF pads CB:43454 - tiogapass: undo set trig and bufdis for NF pads CB:43561 - h110m: undo set trig and bufdis for NF pads CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG Change-Id: Icdb6cb39934548e125461929701b33477a74f2a2 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43454 Reviewed-by: Michael Niewöhner Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26mb/x/acpi_tables: Do minor cleanup on includesKyösti Mälkki
Change-Id: I7a6ddf95d085490d52e00ade7bac23e8c8849427 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42865 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24mb/ocp/tiogapass: Use macro to configure IIOMaxim Polyakov
Use macros to configure each of the IIO ports instead of an array of some unknown parameters. This will clean up the code and make it easier to read. Tested with BUILD_TIMELESS=1, Tioga Pass, remains identical. Change-Id: I2911992435a6c93624525426d56212f821abb866 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43502 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24mb/ocp/deltalake: Send OEM IPMI command for CMOS clear on RTC failureJingle Hsu
When RTC failure is detected, send IPMI OEM command to issue CMOS clear. This is to let the payload (LinuxBoot) handle the IPMI OEM CMOS clear command by resetting RTC data, erasing RW_VPD (TODO) and add a SEL, then reboot the system. Tested=on OCP Delta Lake, after removing RTC battery we can see the above flow can be executed correctly. Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com> Change-Id: I27428c02e99040754e15e07782ec1ad8524def2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/43005 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMCJohnny Lin
1. Populate SMBIOS data from OCP_DMI driver read from FRU 2. Set the read PPIN MSR for CPU0 and CPU1 to BMC, selecting PARALLEL_MP_AP_WORK to enable OCP DMI driver to read remote socket PPIN. Tested on OCP Tioga Pass. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: Ie11ab68267438ea9c669c809985c0c2d7578280e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40524 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23mb/ocp/deltalake: Add ipmi POST start command in romstageTimChu
Add function to send POST start command to BMC. This function is used in romstage and the POST end command will be sent in u-root. TEST=Read POST command log in OpenBMC, if command received successfully, message may show as below, root@bmc-oob:~# cat /var/log/messages |grep -i "POST" 2020 Jul 15 16:36:11 bmc-oob. user.info fby3-v2020.23.1: ipmid: POST Start Event for Payload#2 root@bmc-oob:~# Signed-off-by: TimChu <Tim.Chu@quantatw.com> Change-Id: Ide0e2a52876db555ed8b5e919215e85731fd80ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/41605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-23mb/ocp/deltalake: Implement SMBIOS type 9 -- system slots by SKUMorgan Jang
Create SMBIOS type 9 by getting PCIe config from BMC. TEST=Check SMBIOS type 9 is created correctly on different SKUs Change-Id: Ifd2031b91c960ff2add8807247271eb7c38a0bf2 Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-22mb/ocp/deltalake: Unset POWER_STATE_DEFAULT_ON_AFTER_FAILURETim Chu
Change PCH power policy. Set default of POWER_STATE_DEFAULT_ON_AFTER_FAILURE to n in order to change power state to S5 when power is reapplied after power failure. TEST=Base on CB:42289, CB:43338 and build for Deltalake. The following Kconfig options must be selected: select SOC_INTEL_COMMON_BLOCK_PMC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select CPU_INTEL_COMMON_SMM Boot the system and check the last bit of GEN_PMCON_B is set to 1 through ITP with command: pch.pm_dump Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I4d4f14bdfc18740976171fd5d369b2d79a916dc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42976 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-22mb/ocp/deltalake: Set FSP log level and add default values if VPD variables ↵Johnny Lin
are not found 1. Read VPD variable 'fsp_log_level' to decide FSP log level. 2. Define the default values when the VPD variables cannot be found, put all the values to vpd.h for better documentation and maintenance. Tested=On OCP DeltaLake, the fsp_log_level can be changed from the VPD variable. Change-Id: I44cd59ed0c942c31aaf95ed0c8ac78eb7d661123 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-16Revert "mb/ocp/deltalake: Select IPMI OCP to send POST start/end command"Philipp Deppenwiese
This reverts commit a5ca4a0c75237093f1a4d90f30c0c932e5fcd05d. Reason for revert: Breaks coreboot tree because of non existent kconfig symbol Change-Id: Ib8f55dc2f6444690945bc2dc64baad5d0c39cdf4 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-16mb/ocp/deltalake: Select IPMI OCP to send POST start/end commandTimChu
Implement sending POST start/end command to BMC. TEST=Read POST command log in OpenBMC, if command received successfully, message may show as below, root@bmc-oob:~# cat /var/log/messages |grep -i "POST" 2020 May 28 13:21:22 bmc-oob. user.info fby3-v2020.20.2: ipmid: POST Start Event for Payload#1 2020 May 28 13:21:25 bmc-oob. user.info fby3-v2020.20.2: ipmid: POST End Event for Payload#1 root@bmc-oob:~# Signed-off-by: TimChu <Tim.Chu@quantatw.com> Change-Id: I38b512ee97c0eda6ba54482a448ef9ffc27b4ddb Reviewed-on: https://review.coreboot.org/c/coreboot/+/41993 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16mb/ocp/deltalake: Config PCH PCIe ports in devicetreeMorgan Jang
Tested on OCP Delta Lake with lspci checking if PCIe speed is changed are expected. Change-Id: I189027c403814d68db2b7c5f41fc254a293fe3a1 Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-07-12mb/ocp/deltalake: Pull POST complete pin low before booting payloadJohnny Lin
Delta Lake uses GPIO pin GPP_B20 for POST complete event, BIOS needs to pull this pin low for BIC (Bridge IC) to start reading sensors. Tested=On Delta Lake oBMC, bic-util slotx --get_gpio to confirm the pin is low. Change-Id: I7e05f8a7caead8ee0632af4ff60ccd8b2412b3dd Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-12mb/ocp/deltalake: Use VPD data to configure FSP UPD at romstageJohnny Lin
Read VPD variable 'fsp_log_enable' to decide enabling FSP log or not. With VPD_RW_THEN_RO, VPD_RW takes precedence over VPD_RO, and would be set to enabled if both places cannot find it. Tested=On OCP Delta Lake, use vpd to create and set fsp_log_enable and verified the results are expected. Change-Id: I0b3463acedd90e8e17f7e4eedc2fab63644f87e1 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: insomniac <insomniac@slackware.it>
2020-07-08mb/ocp/deltalake: Enable LPC IO 0x600 decode for BICBryant Ou
BIC uses LPCflash utility to flash FW, it uses LPC to send the bridge IC image from host to bridge IC, 0x600 ~ 0x6FF is used to send BIC image for in-band update support. TEST=Use LPCflash utility to flash BIC FW on YV3 successfully. [root@localhost lpcflash_101_bin]# ./lpc_update.sh Y3BRDL_D06.bin Update Bridge IC Firmware from LPC Deltalake linux utility ver:1.01 build time: Feb 11 2020 14:30:55 Processing image file: Y3BRDL_D06.bin .. of size 206968 (0x00032878) bytes .. file will be padded to a 64-byte size .. with DEBUG Enabled Generating CRC-32 for file. Done (0x4e3905a3). iBytesRead (0x00007c00). Discovering LPC boot loader. Discovered @ 0x3f8. Configuring LPC boot loader. Configured @ 0x00000600. Sending header block. Sent. Loading firmware into target. Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 16512 bytes ................. Load complete. Update done! Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com> Change-Id: Ia1ea9b35b154225fdfd8955830e6c42b453a81ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/42856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-08mb/ocp/deltalake: Configure IPMI FRB2 watchdog timer via VPD variables in ↵Johnny Lin
romstage Add VPD variables for enabling/disabling FRB2 watchdog timer and setting the timer countdown value. By default it would start the timer and trigger hard reset when it's expired. The timer is expected to be stopped later by payload or OS. Tested on OCP Delta Lake. Change-Id: I3ce3bdc24a41d27eb1877655b3148ba02f7f5497 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-08mb/ocp/deltalake: Update IIO PCIe bifurcation according to different configsJohnny Lin
In romstage get the config from BMC IPMI and update the IIO accordingly. Tested on OCP Delta Lake with FSP WW24 release, with lspci checking bifurcation register values are expected. Change-Id: I412336c32d093fe2bbdc7175f8e596923c77876f Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-07vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt socJonathan Zhang
CPX-SP FSP ww26 release added UPDs to allow FSP serial redirection. Also update memory map HOB definition file accordingly. The CPX-SP soc code is updated to direct FSP log to SOL. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ifd86fb710a0b2bdc8a43225b50b24f585d320caf Reviewed-on: https://review.coreboot.org/c/coreboot/+/42840 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04mb/ocp/deltalake: Add VPD flash regions and select VPD and VPD_SMBIOS_VERSIONJohnny Lin
Tested on OCP Delta Lake. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I1e6e2bd25cbe3b0c0547dda9e457c4d55df28388 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42428 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04mb/ocp/deltalake: Update SMBIOS type 2 Location In Chassis from BMCJohnny Lin
There are 4 slots in YV3, Location In Chassis should be 1~4. Tested=on OCP Delta Lake, dmidecode -t 2 verified the string is correct. Change-Id: I3b65ecc6f6421d85d1cb890c522be4787362a01b Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-04mb/ocp/deltalake: Populate SMBIOS data and set the read PPIN to BMCJohnny Lin
1. Populate SMBIOS data from OCP_DMI driver read from FRU and PPIN MSR for OEM string 1 to 6, add string 8 for PCIE configuration. 2. Set the read PPIN MSR to BMC. Tested on OCP Delta Lake. Change-Id: I9127cf5da1c56d8012694d070615aec24cc22fdf Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41279 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-02mb/ocp: remove sonorapassJonathan Zhang
Sonora Pass server program was terminated. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I5354ea1e912fd25f0ac9851edf0461413ad8bb21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42948 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30ACPI: Drop typedef global_nvs_tKyösti Mälkki
Bring all GNVS related initialisation function to global scope to force identical signatures. Followup work is likely to remove some as duplicates. Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25mb/ocp/deltalake: Enable IPMI KCSMorgan Jang
Config the IO port for IPMI KCS and set bmc_boot_timeout for checking BMC self test result. TEST=Check if the BMC IPMI reponse data is correct or not. Change-Id: I675060299b486986ebc39d8f714615b3e13de89a Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41023 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/ocp/deltalake: add RW_MRC_CACHE flash regionJonathan Zhang
Add RW_MRC_CACHE flash region to hold MRC cache data. With memory training skipped for subsequent reboots, the boot time is reduced by 8 minutes on OCP Delta Lake server, when FSP verbose logging is turned on. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I27ed00100e1ea9e29b0e71ea5a8397cd550e193a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42025 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/ocp/deltalake: Add OCP Delta Lake mainboardJonathan Zhang
OCP Delta Lake server is a one socket server platform powered by Intel Cooper Lake Scalable Processor. The Delta Lake server is a blade of OCP Yosemite V3 multi-host sled. TESTED=Successfully booted on both YV3 config A Delta Lake server and config C Delta Lake server. The coreboot payload is Linux kernel plus u-root as initramfs. Below are the logs of ssh'ing into a config C deltalake server: jonzhang@devvm2573:~$ ssh yv3-cth root@ip's password: Last login: Mon Apr 20 21:56:51 2020 from [root@dhcp-100-96-192-156 ~]# lscpu Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 52 On-line CPU(s) list: 0-51 ... [root@dhcp-100-96-192-156 ~]# cbmem 34 entries total: 0:1st timestamp 28,621,996 40:device configuration 178,835,602 (150,213,605) ... Total Time: 135,276,123,874,479,544 [root@dhcp-100-96-192-156 ~]# cat /proc/cmdline root=UUID=f0fc52f2-e8b8-40f8-ac42-84c9f838394c ro crashkernel=auto selinux=0 console=ttyS1,57600n1 LANG=en_US.UTF-8 earlyprintk=serial,ttyS0,57600 earlyprintk=uart8250,io,0x2f8,57600n1 console=ttyS0,57600n1 loglevel=7 systemd.log_level=debug Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: I0a5234d483e4ddea1cd37643b41f6aba65729c8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-19Kconfig: Escape variable to accommodate new Kconfig versionsPatrick Georgi
Kconfig 4.17 started using the $(..) syntax for environment variable expansion while we want to keep expansion to the build system. Older Kconfig versions (like ours) simply drop the escapes, not changing the behavior. While we could let Kconfig expand some of the variables, that only splits the handling in two places, making debugging harder and potentially messing with reproducible builds (e.g. when paths end up in configs), so escape them all. Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-06-07acpi: Rename motherboard_fill_fadt() to mainboard_fill_fadt()Kyösti Mälkki
The prefix mainboard_ was used everywhere else. Change-Id: Ie576fd47301aa484cb1396e0c6f7260b7698af4d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-07mb/*: Remove some fadt.c filesKyösti Mälkki
Change-Id: I13ed3b6e8608c37c1ebe51838e4052f89a638d83 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41947 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-10src/mainboard: Replace GPLv2 long form headers with SPDX headerElyes HAOUAS
Change-Id: I64d9468682a4aae3084b17b8724d035f17d01dff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-06treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi
This replaces GPLv2-or-later and GPLv2-only long form text with the short SPDX identifiers. Commands used: perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi
That makes it easier to identify "license only" headers (because they are now license only) Script line used for that: perl -i -p0e 's|/\*.*\n.*This file is part of the coreboot project.*\n.*\*|/* This file is part of the coreboot project. */\n/*|' # ...filelist... Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-01md/tiogapass: move all *.h to dir and make them globalMaxim Polyakov
It is necessary to rename the file gpio.h so that there are no conflict with another file (src/include/gpio.h) Change-Id: I4e3ef5882d6cb0ddbcb8357b54106ff2f47e4c51 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40733 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01xeon_sp, ocp/tiogapass: remove unused FSP-style GPIO defsMaxim Polyakov
Change-Id: I8599dca99c1f34e3937c5b77b3505815ce625b46 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01mb/ocp/tiogapass: fix advanced _PAD_CFG_STRUCT macros in configMaxim Polyakov
If the current pad configuration can not be defined using standard macros from the gpio_defs.h [1], then the intelp2m utility generates "advanced" _PAD_CFG_STRUCT() macros. However, often this configuration in the vendor’s firmware is erroneous. Change the extended macros to standard ones taking into account the information based on the schematic diagram and the previous GPIO configuration for FSP-M [2]. [1] src/soc/intel/common/block/include/intelblocks/gpio_defs.h [2] src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h Change-Id: I56e45b1df77acbdd67e6325c3745a7ad137f8805 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
2020-05-01mb/ocp/tiogapass: rework GPIOs configuration using macrosMaxim Polyakov
This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. The gpio.h file with PAD_CFG macros was automatically generated using the util/intelp2m [1] utility: ./intelp2m -p lbg -file tiogapass/vendorbios/inteltool_gpio.log According to the documentation [2], the Host Software Pad Ownership register only affects the pads that are configured as input (GPI). The intelp2m utility takes this into account when converting macros and ignores bits from this register for the corresponding pads. [1] https://review.coreboot.org/c/coreboot/+/35643 [2] Intel Document Number: 549921 Change-Id: I21e98721e58b00be9196927837daa2b5d2560822 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40731 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01mb/tiogapass: use common driver to configure GPIOMaxim Polyakov
According to changes in the soc/xeon_sp code [1,2], server motherboards with Lewisburg PCH can use the soc/intel/common/gpio driver to configure GPIO controller. This patch adds pads configuration map, which has the format required by the GPIO driver. The data for this was taken from the inteltool register dump with AMI firmware. The gpio.h file with pad configuration was generated automatically using the util/intelp2m [3]: ./intelp2m -raw -p lbg -file tiogapass/vendorbios/inteltool_gpio.log [1] https: //review.coreboot.org/c/coreboot/+/39425 [2] https: //review.coreboot.org/c/coreboot/+/39428 [3] https: //review.coreboot.org/c/coreboot/+/35643 Change-Id: I818d040fa33f3e7b94b73c9bbbafca5df424616d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39427 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01mb/ocp/sonorapass: Populate FSP-M parametersAndrey Petrov
Since CPX FSP headers are not released yet, populate certain settings with hard-coded offsets. Provided values are probably not correct and I do not understand what they mean and there is no documentation available yet. However they were found to work to a certain degree. TEST=tested on OCP Sonora Pass EVT Change-Id: I0f78cde69cb8a49a388a412b97bf8713e5b380ea Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40554 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01mb/ocp/sonorapass: Add Sonora PassRyback Hung
Just a minimal set of board files needed to get it to boot in 1 CPU mode. Signed-off-by: Ryback Hung <ryback.hung%quantatw.com@gtempaccount.com> Change-Id: Ia7b45c78b38d091bd9535899b681746e13efb4fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/40469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
2020-05-01mb/ocp/tiogapass: Update UPD IIO bifurcation at run-timeJohnny Lin
Update UPD IIO bifurcation at run-time according to different Riser cards. For detail please reference Facebook Server Intel Motherboard v4.0, Sec. 10.1.2 Riser card types. With the engineering build FSP, it can only configure IIO for one socket so my local test needs to remove all socket1 elements from tp_iio_bifur_table. This change relies on [1] and need to add GPP_C15 and GPP_C16 to early_gpio_table for gpio configuration in bootblock. [1] https://review.coreboot.org/c/coreboot/+/39427/ Tested=OCP Tioga Pass can see socket0 IIO being updated with an engineering build FSP. Change-Id: I8e63a233a2235cd45b14b20542e6efab3de17899 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-04-30mb/ocp/tiogapass: Implement port 80h direct to GPIO and init UART pinsBryantOu
Enable aspeed's function that port 80h direct to GPIO for LED display, refer to section 9.4 Port 80h Direct to GPIO Guide of aspeed's Application Design Guide, also configure GPIO to UART for output serial console messages. Tested=Check if port 80h LED debug card can display POST codes at early stage, and serial console can see the related messages. Change-Id: I087d5a81b881533b4550c193e4e9720a134fb8e7 Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40481 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-18mb/ocp/tiogapass: Pull POST complete pinBryantOu
Tioga Pass platform use GPIO pin of GPP_B20 for POST complete, BIOS needs to configure this pin for BMC to poll, so it knows when to start to access other components. Tested=Read GPIO status (GPIOAA7) in OpenBMC, the value is 0, the command and result are shown as below, root@bmc-oob:~# cat /tmp/gpionames/FM_BIOS_POST_CMPLT_N/value 0 root@bmc-oob:~# Change-Id: I134f80153461c5acd872587038a2207586b658dd Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 08:54:29 +0000