coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2018-05-31	cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDE	Nico Huber
	As far as I can see this Kconfig option was used wrong ever since it was added. According to the commit message of 107f72e (Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR), it was only necessary to prevent overlapping with CAR. Let's handle the potential overlap in C macros instead and get rid of that option. Currently, it was only used by most FSP1.0 boards, and only because the `fsp1_0/Kconfig` set it to CBFS_SIZE (WTF?). Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-05	mainboard/ocp/wedge100s: Initial commit	David Hendricks
	This patch does the following: 1. Copy src/mainboard/intel/camelbackmountain_fsp to src/mainboard/ocp/wedge100s. 2. Update Kconfig files 3. Add board.fmd 4. Enable VPD The OCP Wedge100S is a 100GbE top-of-rack switch with a Xeon D-1500 com-express module. More info is available at http://www.opencompute.org/wiki/Networking/SpecsAndDesigns. Signed-off-by: Sudhakar Mamillapalli <sudhakar@fb.com> Signed-off-by: David Hendricks <dhendricks@fb.com> Change-Id: Ia150b066124953c7c0abe8ea5a13e4131194ea00 Reviewed-on: https://review.coreboot.org/25671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>