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CPX-SP FSP ww26 release added UPDs to allow FSP serial redirection. Also
update memory map HOB definition file accordingly.
The CPX-SP soc code is updated to direct FSP log to SOL.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ifd86fb710a0b2bdc8a43225b50b24f585d320caf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42840
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested on OCP Delta Lake.
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: I1e6e2bd25cbe3b0c0547dda9e457c4d55df28388
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42428
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There are 4 slots in YV3, Location In Chassis should be 1~4.
Tested=on OCP Delta Lake, dmidecode -t 2 verified the string is correct.
Change-Id: I3b65ecc6f6421d85d1cb890c522be4787362a01b
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
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1. Populate SMBIOS data from OCP_DMI driver read from FRU and PPIN MSR
for OEM string 1 to 6, add string 8 for PCIE configuration.
2. Set the read PPIN MSR to BMC.
Tested on OCP Delta Lake.
Change-Id: I9127cf5da1c56d8012694d070615aec24cc22fdf
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41279
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Config the IO port for IPMI KCS and set bmc_boot_timeout for checking BMC self test result.
TEST=Check if the BMC IPMI reponse data is correct or not.
Change-Id: I675060299b486986ebc39d8f714615b3e13de89a
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41023
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add RW_MRC_CACHE flash region to hold MRC cache data.
With memory training skipped for subsequent reboots, the boot
time is reduced by 8 minutes on OCP Delta Lake server, when
FSP verbose logging is turned on.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I27ed00100e1ea9e29b0e71ea5a8397cd550e193a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42025
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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OCP Delta Lake server is a one socket server platform powered by
Intel Cooper Lake Scalable Processor.
The Delta Lake server is a blade of OCP Yosemite V3 multi-host
sled.
TESTED=Successfully booted on both YV3 config A Delta Lake server
and config C Delta Lake server. The coreboot payload is Linux kernel
plus u-root as initramfs. Below are the logs of ssh'ing into a
config C deltalake server:
jonzhang@devvm2573:~$ ssh yv3-cth
root@ip's password:
Last login: Mon Apr 20 21:56:51 2020 from
[root@dhcp-100-96-192-156 ~]# lscpu
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 52
On-line CPU(s) list: 0-51
...
[root@dhcp-100-96-192-156 ~]# cbmem
34 entries total:
0:1st timestamp 28,621,996
40:device configuration 178,835,602 (150,213,605)
...
Total Time: 135,276,123,874,479,544
[root@dhcp-100-96-192-156 ~]# cat /proc/cmdline
root=UUID=f0fc52f2-e8b8-40f8-ac42-84c9f838394c ro crashkernel=auto selinux=0 console=ttyS1,57600n1 LANG=en_US.UTF-8 earlyprintk=serial,ttyS0,57600 earlyprintk=uart8250,io,0x2f8,57600n1 console=ttyS0,57600n1 loglevel=7 systemd.log_level=debug
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I0a5234d483e4ddea1cd37643b41f6aba65729c8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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