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2020-07-12mb/ocp/deltalake: Pull POST complete pin low before booting payloadJohnny Lin
Delta Lake uses GPIO pin GPP_B20 for POST complete event, BIOS needs to pull this pin low for BIC (Bridge IC) to start reading sensors. Tested=On Delta Lake oBMC, bic-util slotx --get_gpio to confirm the pin is low. Change-Id: I7e05f8a7caead8ee0632af4ff60ccd8b2412b3dd Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-12mb/ocp/deltalake: Use VPD data to configure FSP UPD at romstageJohnny Lin
Read VPD variable 'fsp_log_enable' to decide enabling FSP log or not. With VPD_RW_THEN_RO, VPD_RW takes precedence over VPD_RO, and would be set to enabled if both places cannot find it. Tested=On OCP Delta Lake, use vpd to create and set fsp_log_enable and verified the results are expected. Change-Id: I0b3463acedd90e8e17f7e4eedc2fab63644f87e1 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: insomniac <insomniac@slackware.it>
2020-07-08mb/ocp/deltalake: Enable LPC IO 0x600 decode for BICBryant Ou
BIC uses LPCflash utility to flash FW, it uses LPC to send the bridge IC image from host to bridge IC, 0x600 ~ 0x6FF is used to send BIC image for in-band update support. TEST=Use LPCflash utility to flash BIC FW on YV3 successfully. [root@localhost lpcflash_101_bin]# ./lpc_update.sh Y3BRDL_D06.bin Update Bridge IC Firmware from LPC Deltalake linux utility ver:1.01 build time: Feb 11 2020 14:30:55 Processing image file: Y3BRDL_D06.bin .. of size 206968 (0x00032878) bytes .. file will be padded to a 64-byte size .. with DEBUG Enabled Generating CRC-32 for file. Done (0x4e3905a3). iBytesRead (0x00007c00). Discovering LPC boot loader. Discovered @ 0x3f8. Configuring LPC boot loader. Configured @ 0x00000600. Sending header block. Sent. Loading firmware into target. Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 16512 bytes ................. Load complete. Update done! Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com> Change-Id: Ia1ea9b35b154225fdfd8955830e6c42b453a81ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/42856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-08mb/ocp/deltalake: Configure IPMI FRB2 watchdog timer via VPD variables in ↵Johnny Lin
romstage Add VPD variables for enabling/disabling FRB2 watchdog timer and setting the timer countdown value. By default it would start the timer and trigger hard reset when it's expired. The timer is expected to be stopped later by payload or OS. Tested on OCP Delta Lake. Change-Id: I3ce3bdc24a41d27eb1877655b3148ba02f7f5497 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-08mb/ocp/deltalake: Update IIO PCIe bifurcation according to different configsJohnny Lin
In romstage get the config from BMC IPMI and update the IIO accordingly. Tested on OCP Delta Lake with FSP WW24 release, with lspci checking bifurcation register values are expected. Change-Id: I412336c32d093fe2bbdc7175f8e596923c77876f Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-07vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt socJonathan Zhang
CPX-SP FSP ww26 release added UPDs to allow FSP serial redirection. Also update memory map HOB definition file accordingly. The CPX-SP soc code is updated to direct FSP log to SOL. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ifd86fb710a0b2bdc8a43225b50b24f585d320caf Reviewed-on: https://review.coreboot.org/c/coreboot/+/42840 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04mb/ocp/deltalake: Add VPD flash regions and select VPD and VPD_SMBIOS_VERSIONJohnny Lin
Tested on OCP Delta Lake. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I1e6e2bd25cbe3b0c0547dda9e457c4d55df28388 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42428 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04mb/ocp/deltalake: Update SMBIOS type 2 Location In Chassis from BMCJohnny Lin
There are 4 slots in YV3, Location In Chassis should be 1~4. Tested=on OCP Delta Lake, dmidecode -t 2 verified the string is correct. Change-Id: I3b65ecc6f6421d85d1cb890c522be4787362a01b Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-04mb/ocp/deltalake: Populate SMBIOS data and set the read PPIN to BMCJohnny Lin
1. Populate SMBIOS data from OCP_DMI driver read from FRU and PPIN MSR for OEM string 1 to 6, add string 8 for PCIE configuration. 2. Set the read PPIN MSR to BMC. Tested on OCP Delta Lake. Change-Id: I9127cf5da1c56d8012694d070615aec24cc22fdf Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41279 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25mb/ocp/deltalake: Enable IPMI KCSMorgan Jang
Config the IO port for IPMI KCS and set bmc_boot_timeout for checking BMC self test result. TEST=Check if the BMC IPMI reponse data is correct or not. Change-Id: I675060299b486986ebc39d8f714615b3e13de89a Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41023 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/ocp/deltalake: add RW_MRC_CACHE flash regionJonathan Zhang
Add RW_MRC_CACHE flash region to hold MRC cache data. With memory training skipped for subsequent reboots, the boot time is reduced by 8 minutes on OCP Delta Lake server, when FSP verbose logging is turned on. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I27ed00100e1ea9e29b0e71ea5a8397cd550e193a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42025 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/ocp/deltalake: Add OCP Delta Lake mainboardJonathan Zhang
OCP Delta Lake server is a one socket server platform powered by Intel Cooper Lake Scalable Processor. The Delta Lake server is a blade of OCP Yosemite V3 multi-host sled. TESTED=Successfully booted on both YV3 config A Delta Lake server and config C Delta Lake server. The coreboot payload is Linux kernel plus u-root as initramfs. Below are the logs of ssh'ing into a config C deltalake server: jonzhang@devvm2573:~$ ssh yv3-cth root@ip's password: Last login: Mon Apr 20 21:56:51 2020 from [root@dhcp-100-96-192-156 ~]# lscpu Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 52 On-line CPU(s) list: 0-51 ... [root@dhcp-100-96-192-156 ~]# cbmem 34 entries total: 0:1st timestamp 28,621,996 40:device configuration 178,835,602 (150,213,605) ... Total Time: 135,276,123,874,479,544 [root@dhcp-100-96-192-156 ~]# cat /proc/cmdline root=UUID=f0fc52f2-e8b8-40f8-ac42-84c9f838394c ro crashkernel=auto selinux=0 console=ttyS1,57600n1 LANG=en_US.UTF-8 earlyprintk=serial,ttyS0,57600 earlyprintk=uart8250,io,0x2f8,57600n1 console=ttyS0,57600n1 loglevel=7 systemd.log_level=debug Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: I0a5234d483e4ddea1cd37643b41f6aba65729c8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 20:20:31 +0000