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2024-08-06mb/msi/ms7d25,ms7e06: Enable discrete TPM module supportMichał Żygowski
Now that multiple TPM drivers may be compiled in, it is possible to support switching between fTPM and dTPM. The patch adds: - Device tree entry for PC80 discrete TPM - TPM PIRQ# GPIO active low routed to IOAPIC for TPM interrupt - MEMORY_MAPPED_TPM option to board's Kconfig to enable PC80 TPM driver When the ME is disabled, e.g. via HECI command, chipset will route the TPM traffic to SPI automatically. When a SPI TPM is connected to the JTPM1 on the board, it will be probed successfully and initialized in place of inactive PTT/fTPM. Change-Id: Ie6e7026b6f1cec842bce4ef40b6db7feb75200e3 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80456 Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-07mb/**/hda_verb: Use `AZALIA_PIN_CFG_NC(0)`Angel Pons
Replace `0x411111f0` with `AZALIA_PIN_CFG_NC(0)`, which evaluates to the same value and conveys additional information to the reader. Done with a bulk search and replace operation. Change-Id: Ibd84daec017bc1ab1ee4edd906fda80231c134cc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-30tree: Remove duplicated <soc/gpio.h>Elyes Haouas
<gpio.h> is supposed to chain-include <soc/gpio.h>. Change-Id: Ib25581bd2c8dd38cdd0396561ce5f9a782365f14 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82691 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-30soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZEFelix Singer
Alderlake and Raptorlake SoCs support DDR4 and DDR5, which have a total SPD size of 512 bytes. Set this as the default and remove the setting from mainboard Kconfigs. Change-Id: I8703ec25454a0cd55a3de70f73d2117285a833ae Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82115 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-09tree: Drop unused <console/console.h>Elyes Haouas
Change-Id: Ib1a8fc50217c84e835080c70269ff50fc001392c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81811 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-26mb/msi: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I4a678b433e3e1a492e2a8e679caf75f4741317cb Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81485 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18mb/inventec to mb/ocp: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Ib1bbf22480783f63fc2d729b94251e755d2f1720 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80593 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24mb/lenovo to mb/squared: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4790adb41cb62c8c8dd44261a2926dfb6350955a Reviewed-on: https://review.coreboot.org/c/coreboot/+/80111 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-09-01mb/msi/ms7d25: Configure ASPM and Clock PM based on KconfigMichał Żygowski
Add support for FSP ASPM and Clock PM configuration based on Kconfig options: PCIEXP_ASPM, PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE. For some use cases it may be desirable to disable ASPM and Clock PM to achieve more deterministic and higher performance of PCIe devices. TEST=Boot MSI PRO Z690-A DDR4 without ASPM and Clock PM. Confirm all PCIe devices are still working and ASPM and Clock PM capabilities are not present on the PCIe Root Ports. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I6d9d11016bed89dcfee6909d0d3e3e2e56237a2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69825 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-17mb/msi/ms7d25: Disable DMI ASPMMichał Żygowski
Disable DMI link ASPM which can degrade performance of overall system. Desktop does not need to be concerned that much about idle power consumption. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I60af9d2ab2913db449059e1e007999fa2f307f5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69826 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-23mb/msi/ms7d25/vboot-rwab.fmd: Add 32KiB HSPHY cache regionMichał Żygowski
Add the HSPHY region required by INCLUDE_HSPHY_IN_FMAP option. It is needed in case CSME/HECI is disabled or not visible to keep the PCIe 5.0 root ports functional. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ic4793fc9457f58e914ef3e18cce1294f230462bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/68988 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-31mb/msi/ms7d25: Add console die notificationMichał Żygowski
Add beeps and blink SATA LED on critical errors. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I45b8b4fda00d58a1ab1d7dfab49d6f841bc0b000 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69821 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22mb/msi/ms7d25: Re-enable GpioOverrideMichał Żygowski
Set all GPIOs to their target functions and do not depend on FSP to configure them. The board support has stabilized and was tested with many PCIe devices. There is no need to detect CLKREQ signals so we may hardcode them. TEST=Boot MSI PRO Z690-A DDR4 to Linux and check if all ASPM and Clock PM features' state on PCIe root ports are the same before and after the change. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I01dc83ce23ca27525b8905665da942510f249824 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-22mb/msi/ms7d25: Disable PCIe hotplugMichał Żygowski
The support for the board has stabilized and PCIe ports have been tested with many devices. Although hotplug is not commonly used and it seems pointless to keep it enabled, so disable it. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I338c55cb57d971badd08235b71626a710fafb829 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-15mb/msi/ms7d25: Update USB port macrosMichał Żygowski
Update USB port macros: - change onboard ports to SHORT: MYSTIC LIGHT, LAN_USB1, PS2_USB1, HUB to USB 2.0 headers, HUB to rear USB 2.0 - change USB type C header to LONG which caused hard lockups on the port making it unable to enumerate in UEFI Payload and Linux - add empty definitions for USBr ports Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I91198aa713e9084ff3906c267ee1b37b10c71843 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69820 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-05Convert literal uses of CONFIG_MAINBOARD_{VENDOR,PART_NUMBER}Kyösti Mälkki
Only expand these strings in lib/identity.o. Change-Id: I8732bbeff8cf8a757bf32fdb615b1d0f97584585 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-26mb/{system76,msi}: Enable PchHdaAudioLinkHdaEnable via devicetreeSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iae2dc0a934f0ea3ca59d8a811f1daeedb090a7bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/71717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2023-03-22mb/msi/ms7d25/gpio.h: add spaces around bitwise or operatorYuchen He
To be consistent with other occurrences, add a space around the bitwise or operator. Signed-off-by: Yuchen He <yuchenhe126@gmail.com> Change-Id: I674311ae330789b75fe7d189ad0fddeae45efe02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-13mb/msi/ms7d25: Add support for DDR5 variantMichał Żygowski
The DDR5 board is almost identical to the DDR4 one. The only major difference is the board's DDR5 memory design. TEST=Boot MSI PRO Z690-A board successfully to Ubuntu 22.04. Memory: Crucial CT8G48C40U5.M4A1 in all 4 slots. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I652a879d1616df4708fe4690797ad98384897f53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-11-20mainboard/msi/ms7d25: Configure NCT6687D pin for PECIMichał Żygowski
One register configuring multi-pin functions was outside of the Global Configuration Registers space and skipped in the initial port patches. Replicate the vendor configuration and set the Super I/O pin for PECI functionality. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I90f142a1a9ee27dd061fc71b791bd4c7df97da6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68711 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-04mb/msi/ms7d25: Populate SMBIOS product name based on CNVi presenceMichał Żygowski
MSI PRO Z690-A WIFI DDR4 and MSI PRO Z690-A DDR4 are basically the same boards, except the latter has no WiFi populated. Check the CNVi WiFi presence and return correct SMBIOS product name string. TEST=Check SMBIOS product name on both WiFi and non-WiFi variants in Linux. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I5fedbce413dfb6a589a406d1e34e3e114ca6a40f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68078 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-16mb/**/dsdt.asl: Drop superfluous commentsAngel Pons
These comments don't add much value, so remove them. Change-Id: I7e9692e3fe82345cb7ddcb11c32841c69768cd36 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66713 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-07-13mainboard/msi/ms7d25/gpio.h: Remove redundant NAF_VWE definitionMichał Żygowski
The NAF_VWE bit definition is already present in src/soc/intel/common/block/include/intelblocks/gpio.h. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I1fe713ee08438be49308f5e777cd466cdbc45d71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-07-11mb/msi/ms7d25: Properly handle CnvDdrRfim parameterMichał Żygowski
CNVi DDR RFIM feature should be reported via _DSM function. Add the generic WiFi device which will generate the proper ACPI code and pass the CnviDdrRfim parameter to FSP by SoC driver. TEST=Connect to WiFi network on Ubuntu. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ice2abe972f38dd819f7f0103f7b9a697096f1cd9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63835 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11mainboard/msi/ms7d25: Add USB macros and port designation commentsMichał Żygowski
Add the comments about port designation after mapping the root hub ports to board connectors. Add macros reflecting the length of the USB signal traces. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ib2e842ef240ab25e2a9f7fa2e0766206fde7943d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-07-11mainboard/msi/ms7d25: Add default vboot configurationMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I9590a33e828906de083cb23c8b647ed2da0750ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/64222 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11mainboard/msi/ms7d25: Add FIVR configurationMichał Żygowski
Reflect the vendor's firmware FIVR settings. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I97b3b4f9470267961c138fea70703606373f6d52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64051 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11mainboard/msi/ms7d25: Fill board-specific SMBIOS dataMichał Żygowski
Add board connectors and headers descriptions to SMBIOS. Specify type 1 and type 2 fields as in vendor firmware. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie64be21ff302274769b77550c29e58d4ea1376d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64050 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11mainboard/msi/ms7d25: Add NCT6687D configurationMichał Żygowski
TEST=Boot Ubuntu 22.04, load nct6687 kernel module and use lm-sensors to display information about sensors on the SIO EC. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I55445a94f0de3510324b12558c4343e819412ac0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63928 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11mainboard/msi/ms7d25: Enable PTTMichał Żygowski
Original firmware ships with PTT enabled by default on poweron. PTT takes priority over SPI/LPC TPM so enable the CRB interface until coreboot implements a way to select the interface and adapt the API to handle any TPM detection. TEST=Boot the board and see PTT is detected by Windows and Linux Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I74dc2c4245388a9f134b27e313ef26124b952594 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63834 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11mb/msi/ms7d25: Configure HD AudioMichał Żygowski
Apply correct configuration of HD Audio. TEST=Launch ubuntu 20.04 and launch a YouTube video, check if microphone detects an input in the system sound settings. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I6acc22aa58f6cc99df1d48d651122e74fe08ec02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63723 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11mb/msi/ms7d25: Configure PCIe Root PortsMichał Żygowski
Add the full PCIe root port configuration. Proper initialization of the root ports depends on the correct GPIO programming including virtual wires. Do not program the CLKREQ signals in coreboot to let FSP detect and configure CLKREQ pads. Otherwise the CLKREQ pads are reprogrammed by FSP despite having GpioOverride=1. The pads that should not be touched by coreboot are left commented in the board GPIO file. CLKREQ reprogramming caused undefined behavior when ASPM and Clock PM was being enabled by coreboot on PCIe endpoints of CPU PCIe x4 slot (coreboot printed a lot of exceptions and simply halted). TEST=Boot the MSI PRO Z690-A DDR4 WiFi with all PCIe/M.2 slots populated and check if they are detected and functional in Linux. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I50199d2caf54509a72c5100acb770bf766327e7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/63656 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-08mb/msi/ms7d25: Enable displaysMichał Żygowski
Add VBT from vendor firmware v5.24 and configure display outputs in devicetree. TEST=Boot TianoCore UEFIPayload and notice the UEFI Shell on the connected display via HDMI or DisplayPort on rear panel. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ide560ade5e29844c2f4310639fe5b76ba91865be Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-07-08mb/msi/ms7d25: Add correct memory init configurationMichał Żygowski
Tested with 4x KINGSTON KF3600C17D4/8GX DIMMs. TEST=Include the microcode from vendor firmware and FSP blob from Intel R&DC. Boot the platform and see ramstage is executing. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I98b9c77d791d18640cb05c133cb0bf14ad22dcdb Reviewed-on: https://review.coreboot.org/c/coreboot/+/63503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-07-07mb/msi/ms7d25: add basic FSP configuration in devicetreeMichał Kopeć
Configure some basic FSP parameters in devicetree for to allow for booting an OS. Change-Id: Iff227c70d0155ac27d6ffa50a069d154bb7fce3c Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63499 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-07-07mb/msi/ms7d25: add GPIO configurationMichał Kopeć
Based on the output of: - inteltool from CB:63374 - intelp2m from CB:63403 TEST=Build coreboot binary for msi/ms7d5 and boot the board. Change-Id: If37eaf875f8fcfc64299227744a8c40d304a0214 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-07-07mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFIMichał Żygowski
Initial mainboard code MSI PRO Z690-A DDR4 WIFI. The platform boots up up to romstage where it returns from FSP memory init with an error. What works: - open-source CAR setup - NCT6687D serial port with TX pin exposed on JBD1 header - SMBus reading SPD from all 4 DIMMs This board will serve as a reference board for enabling Alder Lake-S support in coreboot. More code and functionalities will be added in subsequent patches as src/soc/alderlake code will be improved for PCH-S. TEST=Extract the microcode from vendor firmware and include it in the build. The platform should print the console on the serial port even without FSP blob. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I5df69822dbb3ff79e087408a0693de37df2142e8 Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com> Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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