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CNVi DDR RFIM feature should be reported via _DSM function. Add the
generic WiFi device which will generate the proper ACPI code and
pass the CnviDdrRfim parameter to FSP by SoC driver.
TEST=Connect to WiFi network on Ubuntu.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ice2abe972f38dd819f7f0103f7b9a697096f1cd9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63835
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the comments about port designation after mapping the root hub
ports to board connectors. Add macros reflecting the length of the
USB signal traces.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ib2e842ef240ab25e2a9f7fa2e0766206fde7943d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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Reflect the vendor's firmware FIVR settings.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I97b3b4f9470267961c138fea70703606373f6d52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64051
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TEST=Boot Ubuntu 22.04, load nct6687 kernel module and use lm-sensors
to display information about sensors on the SIO EC.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I55445a94f0de3510324b12558c4343e819412ac0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63928
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Original firmware ships with PTT enabled by default on poweron.
PTT takes priority over SPI/LPC TPM so enable the CRB interface
until coreboot implements a way to select the interface and adapt
the API to handle any TPM detection.
TEST=Boot the board and see PTT is detected by Windows and Linux
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I74dc2c4245388a9f134b27e313ef26124b952594
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63834
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Apply correct configuration of HD Audio.
TEST=Launch ubuntu 20.04 and launch a YouTube video, check if
microphone detects an input in the system sound settings.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I6acc22aa58f6cc99df1d48d651122e74fe08ec02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63723
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the full PCIe root port configuration. Proper initialization of
the root ports depends on the correct GPIO programming including
virtual wires. Do not program the CLKREQ signals in coreboot to let FSP
detect and configure CLKREQ pads. Otherwise the CLKREQ pads are
reprogrammed by FSP despite having GpioOverride=1. The pads that
should not be touched by coreboot are left commented in the board GPIO
file. CLKREQ reprogramming caused undefined behavior when ASPM and
Clock PM was being enabled by coreboot on PCIe endpoints of CPU PCIe
x4 slot (coreboot printed a lot of exceptions and simply halted).
TEST=Boot the MSI PRO Z690-A DDR4 WiFi with all PCIe/M.2 slots
populated and check if they are detected and functional in Linux.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I50199d2caf54509a72c5100acb770bf766327e7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63656
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add VBT from vendor firmware v5.24 and configure display outputs in
devicetree.
TEST=Boot TianoCore UEFIPayload and notice the UEFI Shell on the
connected display via HDMI or DisplayPort on rear panel.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ide560ade5e29844c2f4310639fe5b76ba91865be
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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Configure some basic FSP parameters in devicetree for
to allow for booting an OS.
Change-Id: Iff227c70d0155ac27d6ffa50a069d154bb7fce3c
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63499
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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Initial mainboard code MSI PRO Z690-A DDR4 WIFI. The platform boots up
up to romstage where it returns from FSP memory init with an error.
What works:
- open-source CAR setup
- NCT6687D serial port with TX pin exposed on JBD1 header
- SMBus reading SPD from all 4 DIMMs
This board will serve as a reference board for enabling Alder Lake-S
support in coreboot. More code and functionalities will be added in
subsequent patches as src/soc/alderlake code will be improved for
PCH-S.
TEST=Extract the microcode from vendor firmware and include it in the
build. The platform should print the console on the serial port even
without FSP blob.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5df69822dbb3ff79e087408a0693de37df2142e8
Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com>
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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