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2016-11-07riscv: Unify SBI call implementations under arch/riscv/Jonathan Neuschäfer
Note that currently, traps are only handled by the trap handler installed in the bootblock. The romstage and ramstage don't override it. TEST=Booted emulation/spike-qemu and lowrisc/nexys4ddr with a linux payload. It worked as much as before (Linux didn't boot, but it made some successful SBI calls) Change-Id: Icce96ab3f41ae0f34bd86e30f9ff17c30317854e Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17057 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-11-07mb/lowrisc/nexys4ddr: Actually fix the UART clock setupJonathan Neuschäfer
Ron's code calculated the DLL and DLM registers of the 8250 UART, but that's the job of the UART driver. uart_input_clock_divider isn't needed anymore because the default value of 16 works. As a bonus, the baud rate can now be selected in Kconfig, instead of being hardcoded at 115200. TEST=Booted the board at 9600 and 115200 baud. Change-Id: I3d5e49568b798a6a6d944db1161def7d0a2d3b48 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17188 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-10-28riscv: add the lowrisc/nexys4ddr mainboardRonald G. Minnich
This was tested at the coreboot meeting in Berlin. The uart programming may still not be right but when used with the lowrisc bitstream for the board we were able to load and start linux, although it does not yet get far due to PTE version issues with lowrisc. Change-Id: Ia1de1a92762631c9d7bb3d41b04f95296144caa3 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17132 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)