coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2018-09-26	mb/lowrisc: Remove the Nexys4DDR port	Jonathan Neuschäfer
	This board doesn't support the newest RISC-V Privileged Architecture spec (1.10), and it's based on an FPGA so it's a moving target. Now that there's actual RISC-V silicon out there (from SiFive), mb/lowrisc/nexys4ddr will only continue to bitrot. Change-Id: I4e3e715106a1a94381a563dc4a56781c35883c2d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-06-09	mainboard: Get rid of device_t in ramstage	Elyes HAOUAS
	Use of device_t has been abandoned in ramstage. Change-Id: I07e00afbbd2c19cf3ea6e08f228eb39e45f1ad0c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-02	src/mainboard: Add and update license headers	Martin Roth
	This change adds and updates headers in all of the mainboard files that had missing or unrecognized headers. After this goes in, we can turn on lint checking for headers in all mainboard directories. Change-Id: Ibe038a8f7468253b21fd2ac90c045d0c9cc89dfc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-04-27	RISC-V boards: Remove PAGETABLES section from memlayout.ld	Jonathan Neuschäfer
	RISC-V doesn't set up page tables anymore, since commit b26759d703 ("arch/riscv: Don't set up virtual memory"). Change-Id: Id1e759b63fb0bc88ab256994d3849d16814affa0 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07	RISC-V boards: Stop using the config string	Jonathan Neuschäfer
	RISC-V is moving towards OpenFirmware-derived device trees, and the old functions to read the config string don't work anymore. Use dummy values for the memory base and size until we can query the device tree. Change-Id: Ice13feae4da2085ee56bac4ac2864268da18d8fe Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-06	mb/lowrisc/nexys4ddr: Read RAM information from the config string	Jonathan Neuschäfer
	Change-Id: I9147eca0b536b6267d58f6e8baa37b6950b35160 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17710 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-06	mb/lowrisc/nexys4ddr: Initialize CBMEM in romstage	Jonathan Neuschäfer
	Change-Id: Ic1706ae8ab3cbef8f445d70cb78fa9d3301d87be Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17707 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-11-07	riscv: Unify SBI call implementations under arch/riscv/	Jonathan Neuschäfer
	Note that currently, traps are only handled by the trap handler installed in the bootblock. The romstage and ramstage don't override it. TEST=Booted emulation/spike-qemu and lowrisc/nexys4ddr with a linux payload. It worked as much as before (Linux didn't boot, but it made some successful SBI calls) Change-Id: Icce96ab3f41ae0f34bd86e30f9ff17c30317854e Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17057 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-11-07	mb/lowrisc/nexys4ddr: Actually fix the UART clock setup	Jonathan Neuschäfer
	Ron's code calculated the DLL and DLM registers of the 8250 UART, but that's the job of the UART driver. uart_input_clock_divider isn't needed anymore because the default value of 16 works. As a bonus, the baud rate can now be selected in Kconfig, instead of being hardcoded at 115200. TEST=Booted the board at 9600 and 115200 baud. Change-Id: I3d5e49568b798a6a6d944db1161def7d0a2d3b48 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17188 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-10-28	riscv: add the lowrisc/nexys4ddr mainboard	Ronald G. Minnich
	This was tested at the coreboot meeting in Berlin. The uart programming may still not be right but when used with the lowrisc bitstream for the board we were able to load and start linux, although it does not yet get far due to PTE version issues with lowrisc. Change-Id: Ia1de1a92762631c9d7bb3d41b04f95296144caa3 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17132 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)