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2017-09-06AGESA f14: Work around soft-resetsKyösti Mälkki
Vendorcode expects some DRAM controller registers to be writable, but they are actually locked after soft resets if C6 states are enabled. Without the workaround, raminit fails on soft resets. Change-Id: I6b9e275e11b2907d026c13341334983a4d9c8889 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06mainboard/lippert: Refactor SEMA watchdog messageKyösti Mälkki
It's too critical to ignore when sending the message on SMBus fails, so allow for a fair amount of retries. Failure here causes watchdog to do hard reset later. Move it out of mainboard.c as we need to call this early in romstage while we are debugging. Change-Id: I1006b079269d6dd44de630db7a5694124af2f974 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-01lippert/toucan-af: Switch away from AGESA_LEGACYKyösti Mälkki
NOTE: Some code was currently left behind that may be required for certain type of board reboots. A followup patch will address this. Change-Id: I8fb89fb82c3a3608bb84b29319eb793605538996 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-01lippert/frontrunner-af: Switch away from AGESA_LEGACYKyösti Mälkki
NOTE: Some code was currently left behind that may be required for certain type of board reboots. A followup patch will address this. Change-Id: I3c1258b4e4dcf6fd04f57f5ab59cb1572a7d1fa3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-23AGESA binaryPI: Consolidate and fix sleep statesKyösti Mälkki
SSFG was meant to be used as a mask to enable sleep states _S1 thru _S4. However as a logical instead of bitwise 'and' operation was used, all the states were enabled if only one was marked available. State _S3 is now set conditionally if HAVE_ACPI_RESUME=y. For pi/hudson this had been fixed already preprocessor. Note that all boards had SSFG == 0x0D that previously enabled ACPI S3 sleep state even when it was not available. States _S1 and _S2 still appear enabled in ASL/AML but may not actually work. TEST: 'cat /sys/power/state' and notice choice 'mem' was removed from the list of available sleep states. Change-Id: I27d616871c1771f0c87d8fba23d4ce1569607765 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-08-16AGESA f14: Sacrifice ACPI S3 support for EARLY_CBMEM_INITKyösti Mälkki
A decision has been made that boards with LATE_CBMEM_INIT will be dropped from coreboot master starting with next release scheduled for October 2017. As existing implementation of CAR teardown in AGESA can only do either EARLY_CBMEM_INIT or ACPI S3 support, choose the former. ACPI S3 support may be brought back at a later date for these platforms but that requires fair amount of work fixing the MTRR issues causing low-memory corruptions. Change-Id: I5d21cf6cbe02ded67566d37651c2062b436739a3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-18sb/amd/cs5536: Remove includes of C filesMartin Roth
The romstage for CS5536 platforms were including early_smbus.c and early_setup.c. Build these into romstage from the makefile, and remove the #includes. Add a Kconfig option for platforms that do not use the early smbus code. Change-Id: I2e6a9cd859292b4dd4720b547d1ff0bbb6c319cf Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-06mainboard/[g-l]: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Change-Id: I1f906c8c465108017bc4d08534653233078ef32d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-04-25AMD Geode: Move conflicting mainboard_romstage_entry()Marc Jones
The silicon specific mainboard_romstage_entry() in amd/cpu/car.h, which is used by all AMD silicon car code, caused a conflict. Move the silicon specific defines to silicon header files. Also, no longer include car.h in the romstage file. Change-Id: Icfc759c4c93c8dfff76f5ef9a1a985dd704cfe94 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18769 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-28AGESA: Introduce AGESA_LEGACY and its counterpartKyösti Mälkki
We define AGESA_LEGACY as an implementation of mainboard that has its romstage main completely under mainboard/ directory. We have learnt from other platforms this approach has several downsides when it comes to making platform-wide improvements. We start by creating per-family romstage.c file, which boards will gradually take into use by removing the AGESA_LEGACY Kconfig option we here apply to all of them. Change-Id: Id01931e185a023039a60af16a678de9966db8d65 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18619 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-08AMD geode: Avoid conflicting main() declarationKyösti Mälkki
Declaration of main in cpu/amd/car.h conflicts with the definition of main required for x86/postcar.c in main_decl.h. Change-Id: I19507b89a1e2ecf88ca574c560d4a9e9a3756f37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18615 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-07AGESA: Add agesa_helper.h headerKyösti Mälkki
These definitions do not require AGESA.h include, and we will eventually remove agesawrapper.h files. Change-Id: I1b5b78409828aaf2616e177bb54a054960c3869f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18588 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-07AGESA: Remove leftover s3resume includeKyösti Mälkki
Change-Id: I7a1574259f73a52b66d03c686ae8ab70345c36ed Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18586 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-07AGESA fam14: Sanitize headerfileKyösti Mälkki
This file is only static defines. Change-Id: Id50a0eba1ce240df36da9bd6b2f39a263fa613df Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18585 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-03-07AGESA: Remove leftover agesawrapper includeKyösti Mälkki
Change-Id: Ib37989ee7535e59b1903537995f8383d8b04387c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18584 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-26amd-based mainboards: Fix whitespace in _PTS commentsMarshall Dawson
Correct tabs that were intended as spaces. Change-Id: Idcf33d829f87a866b5ed880527102918d5b93842 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/17905 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-12-06cpu/amd/mtrr.h: Drop excessive includesKyösti Mälkki
Change-Id: Id404bdab1f2361f1e7d20f7ee72111971863dddf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17736 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06cpu/x86/msr.h: Drop excessive includesKyösti Mälkki
Change-Id: Ic22beaa47476d8c600e4081fc5ad7bc171e0f903 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17735 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01AGESA: Switch to MMCONF_SUPPORT_DEFAULTKyösti Mälkki
Vendorcode always does PCI MMCONF access once it is enabled via MSR. In coreboot proper, we don't give opportunity to make pci_read/write calls before PCI MMCONF is enabled via MSR. This happens early in romstage amd_initmmio() for all cores. Change-Id: If31bc0a67b480bcc1d955632f413f5cdeec51a54 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17533 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01AGESA f14: Consolidate early P-states settingKyösti Mälkki
Change-Id: I3feed296b6ff9908e783c1221a8f61d9c548fef4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17564 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01AGESA f14: Consolidate XIP cacheKyösti Mälkki
Do this like fam15tn to reduce code duplication. Change-Id: I064fd27b85be7fb0c9d6918a84fc6f9b17065534 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17563 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-07src/mainboard: Remove unnecessary whitespaceElyes HAOUAS
Change-Id: I35cb7e08d5233aa5a3dbb4631ab2ee4dc9596f98 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16849 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01mainboard/*/*/*/usb.asl: Use tabs for indentsElyes HAOUAS
Change-Id: Id46a0c4ca59dc7224c2eedd674ea3a5486509de1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16824 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-26mainboard/lippert: Use tabs for indentsElyes HAOUAS
Change-Id: If16d55e4ba0702176dc61524915d215ea46c14ba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16686 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-23mainboard/lippert/frontrunner-af: Use tabs for indentsElyes HAOUAS
Change-Id: Id8b60d32d5bdaaa6c693dcf5db992ed975cc2400 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16685 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-23mainboard/lippert/toucan-af: Use tabs for indentsElyes HAOUAS
Change-Id: Ibd1fa89b450d52691dfef5616712f03fd675f123 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16684 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20src/mainboard/lenovo-winent: Add space around operatorsElyes HAOUAS
Change-Id: Iab2a879ebdea9d93ef5eb7e3abf875036c1e1cb4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16641 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-17mainboard: Clean up boot_option/reboot_bits in cmos.layoutNico Huber
Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector code) the reboot counter stored in `reboot_bits` isn't reset on a reboot with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR enabled, later stages (e.g. payload, OS) have to clear the counter too, when they want to switch to normal boot. So change the bits to (h)ex instead of (r)eserved. To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also remove all occurences of the obsolete `last_boot` bit that have sneaked in again since 24391321 (mainboard: Remove last_boot NVRAM option). Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/16157 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-14src/mainboard: Capitalize ROM, RAM, CPU and APICElyes HAOUAS
Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15987 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31mainboard: Format irq_tables.cPaul Menzel
Run the command below to format the files `irq_tables.c` of (mostly AMD) mainboards correctly with GNU indent 2.2.10. ``` $ git grep -l 'if (sum != pirq->checksum) {' | xargs indent -l ``` Fix up the following two checkpatch.pl errors manually. ``` ERROR: that open brace { should be on the previous line #1219: FILE: src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c:129: + uint8_t reg[8] = + { 0x41, 0x42, 0x43, 0x44, 0x60, 0x61, 0x62, 0x63 }; ERROR: that open brace { should be on the previous line #1221: FILE: src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c:131: + uint8_t irq[8] = + { 0x0A, 0X0B, 0X0, 0X0a, 0X0B, 0X05, 0X0, 0X07 }; ``` This is needed, so that follow-up commits, fixing checkpatch.pl errors and warnings, won’t run into conflicts with the git commit hooks, when for example, spaces instead of tabs are used for indentation. Change-Id: If254723f3013377fb3b9b08dd5eca6b76730ec4a Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/15932 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-31Remove extra newlines from the end of all coreboot files.Martin Roth
This removes the newlines from all files found by the new int-015-final-newlines script. Change-Id: I65b6d5b403fe3fa30b7ac11958cc0f9880704ed7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15975 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-18AMD boards: Fix romstage main() declarationKyösti Mälkki
Boards incorrectly used intel include file for AMD board. Change-Id: I6d3172d1aa5c91c989a6ef63066a7cd6f70013f5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15232 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-04AGESA boards: Split dispatcher to romstage and ramstageKyösti Mälkki
The way dispatcher table is set up prevents linker from optimizing unused code away, we currently have raminit in ramstage. Optimize this manually by configuring AGESA_ENTRY booleans for romstage and ramstage separately. This will remove references in FuncParamsInfo and DispatchTable -arrays. All boards now include multi-core dispatcher, it has minimal footprint: AGESA_ENTRY_LATE_RUN_AP_TASK ACPI S3 support depends on HAVE_ACPI_RESUME being enabled: AGESA_ENTRY_INIT_RESUME AGESA_ENTRY_INIT_LATE_RESTORE AGESA_ENTRY_INIT_S3SAVE Disabled for all boards as it was not used: AGESA_ENTRY_INIT_GENERAL_SERVICES Change-Id: I7ec36a5819a8e526cbeb87b04dce4227a1689285 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14417 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-10AGESA boards: Relocate platform memory configKyösti Mälkki
File buildOpts.c is a can of worms, pull platform memory configuration in to OemCustomize.c. This array should be assigned at runtime instead of linking a modified defaults table. Change-Id: I73d9d3fbc165e6c10472e105576d7c40820eaa6a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14528 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-10AGESA boards: Rename files containing OEM configurationKyösti Mälkki
There are other things besides PCIe port configuration that require board specific hooks. Change-Id: I0923651487b9ed5f6f7569ce08e02d993fa5f976 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14527 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-09ASL: Fix HPBA shadowing.Vladimir Serbinenko
Store (HPBA, HPBA) had no effect. Rename one of HPBA to avoid shadowing. Change-Id: I54bfa7bcb3e05c28fe8a257825af56527dbf663e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13622 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-10ACPI: Work around IASL warning reading/writing same registerMartin Roth
The newer versions of IASL are unhappy when an operator has the same object as both source and destination. The warning can be completely disabled with a command line argument, but in general, I'd really rather not just disable warnings. The bits in this register are write 1 to clear, so reading and writing the same register is what we want to do. Instead, store it in a temporary register then write it in a second operation. Fixes warning: dsdt.aml 1396: Store(PWST, PWST) Warning 3023 - ^ Duplicate value in list (Source is the same as Target) Change-Id: I52d73d4431db237be83016d67cd397f31b53d9c6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12691 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10ACPI: Fix IASL Warning about unused method for _OSI checkMartin Roth
According to the ACPI Spec for CondRefOf, the result argument is optional. In all of these locations, it was getting set but not used, creating a warning in new versions of IASL. Since it's an optional argument, just remove it. dsdt.aml 22: if(CondRefOf(\_OSI,Local1)) Warning 3144 - ^ Method Local is set but never used (Local1) Change-Id: I07f49ac5a3708838d1c4a7216dfb11acc415c881 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12692 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02lippert/frontronner-af & toucan-af: Fix IASL warningsMartin Roth
Not all the paths through the _OSC method returned a value. According to the ACPI spec (5.0 & 6.0), bit 2 needs to be set for an unrecognized GUID. Fixes warnings for both platforms: dsdt.aml 1143: Method(_OSC,4) Warning 3115 - ^ Not all control paths return a value (_OSC) dsdt.aml 1143: Method(_OSC,4) Warning 3107 - ^ Reserved method must return a value (Buffer required for _OSC) Change-Id: Ibaf27c5244b1242b4fc1de474c371f54f930dcb6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12530 Tested-by: build bot (Jenkins) Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-23IASL: Enable warnings as errorsMartin Roth
We've actually got more warnings now than when I first tested IASL warnings as errors. Because of this, I'm adding it with the option to have it disabled, in hopes that things won't get any worse as we work on fixing the IASL warnings that are currently in the codebase. - Enable IASL warnings as errors - Disable warnings as errors in mainboards that currently have warnings. - Print a really obnoxious message on those platforms when they build. ***** WARNING: IASL warnings as errors is disabled! ***** ***** Please fix the ASL for this platform. ***** Change-Id: If0da0ac709bd8c0e8e2dbd3a498fe6ecb5500a81 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10663 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-10mainboard/**/irq_tables.c: Remove reference to getpirPatrick Georgi
The obsolete and removed getpir utility remarked in its output that the data is autogenerated. The tool was removed because it wasn't very reliable, so there's no need to point that anymore. Change-Id: I5d624931ba7872b1fefa8fa3c270ae7367e069fa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/12354 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-05mainboard: Remove last_boot NVRAM optionTimothy Pearson
The last_boot NVRAM option was deprecated and removed in commit 3bfd7cc6. Remove the last_boot option from all affected mainboards to eliminate user confusion. Change-Id: I7e201b9cf21dfe5dda156785bad078524098626d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12316 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30AMD mainboards: Fix 64bit BiosCallOuts.cStefan Reinauer
Change-Id: I0f3297dff47dfb44da034ac6f305dcf1981b9de1 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11080 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-24amd/acpi: Clean up SMBus references.Tobias Diedrich
Replace the AMD SMBus section with the equivalent SB800 smbus.asl include or remove already commented-out sections. Verified by running the cpp preprocessor over the DSDTs and diffing the results against this patch. The only change is in src/mainboard/siemens/sitemp_g1p1/dsdt.asl, where someone added RADD and SADD to the OpRegion, but those are unused, so removing them is fine. Change-Id: I074c8a1ed1c9a944d4988752bd0fc42c199c766c Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/10618 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-23SB800-mainboards: use write8 to disable unused GPP CLKFelix Held
don't use non-volatile pointers for MMIO access Change-Id: I9f38012a806e43f2535265f1d25537c59b53904e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/12081 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-09-22coreboot: introduce commonlibAaron Durbin
Instead of reaching into src/include and re-writing code allow for cleaner code sharing within coreboot and its utilities. The additional thing needed at this point is for the utilities to provide a printk() declaration within a <console/console.h> file. That way code which uses printk() can than be mapped properly to verbosity of utility parameters. Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11592 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-06-23lippert/frontrunner-af: 64bit fixesStefan Reinauer
Change-Id: Ia764798c8b58497e2b453bd000dd06816c28f98f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10600 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-23lippert/toucan-af: 64bit fixesStefan Reinauer
Change-Id: I9e7f78587b9d6e87cf77757654da9145d4187625 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10599 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-08Remove empty lines at end of fileElyes HAOUAS
Used command line to remove empty lines at end of file: find . -type f -exec sed -i -e :a -e '/^\n*$/{$d;N;};/\n$/ba' {} \; Change-Id: I816ac9666b6dbb7c7e47843672f0d5cc499766a3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/10446 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-04devicetree: Discriminate device ops scan_bus()Kyösti Mälkki
Use of scan_static_bus() and tree traversals is somewhat convoluted. Start cleaning this up by assigning each path type with separate static scan_bus() function. For ME, SMBus and LPC paths a bus cannot expose bridges, as those would add to the number of encountered PCI buses. Change-Id: I8bb11450516faad4fa33b8f69bce5b9978ec75e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8534 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-05-24AGESA binaryPI boards: Drop annoying commentaryKyösti Mälkki
Same comments were already removed for the latest board, the amd/lamar. Change-Id: Ie244f838409c567c11f7444c9cf17de72e49dbb0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10283 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-10AGESA: Drop unused AGESA_MEM_TABLEKyösti Mälkki
These tables are not referenced anywhere, thus all comments about adjustments are void. Also drop stub AgesaReadSpd that is all commented out. Change-Id: I12233ea0dc4baaf36a75f359c52cc59c9b6dad79 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10143 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-04-18kconfig: automatically include mainboardsStefan Reinauer
This change switches all mainboard vendors and mainboards to be autoincluded by Kconfig, rather than having to be mentioned explicitly. This means, vendor and mainboard directories are becoming more "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree mainboards / components to be built with a given coreboot version (given that the API did not change) Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: Ib68ce1478a2e12562aeac6297128a21eb174d58a Reviewed-on: http://review.coreboot.org/9295 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-03-07AGESA: Use same HeapManager for all BiosCallOutsKyösti Mälkki
We do not allow platforms to mess around with memory layout. Change-Id: I316ff522c8833fa3b7ad20f2c5a9cae21f4174d8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8604 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-05mainboard: Do not redefine DRIVERS_PS2_KEYBOARD Kconfig variableAlexandru Gagniuc
Change-Id: Icc603dfe92360d978221a25ad28517da43942bea Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8498 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-16mainboard/cmos: Kill off unused boot_* parametersTimothy Pearson
Change-Id: I19d6b56e3ac5e6e7946648b97c86a223b748e3bd Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8460 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16mainboard/cmos: Move ECC variables out of fallback mechanism byteTimothy Pearson
Change-Id: Icebc12d8f83494150a7bdd3adcc168d7b48b2e68 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8458 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16mainboard/cmos: Delete obsolete commented parametersTimothy Pearson
Change-Id: Iccad79c142a7fcf89dd0fbebe8c07ad9ef019e91 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8459 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
2015-01-10ACPI: Add acpi_is_wakeup_s3() for romstageKyösti Mälkki
This replaces acpi_is_wakeup_early(). Change-Id: I23112c1fc7b6f99584bc065fbf6b10fb073b1eb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8187 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-06mainboard: Drop print_ implementation from non-romcc boardsStefan Reinauer
Because we had no stack on romcc boards, we had a separate, not as powerful clone of printk: print_*. Back in the day, like more than half a decade ago, we migrated a lot of boards to printk, but we never cleaned up the existing code to be consistent. instead, we worked around the problem with a very messy console.h (nowadays the mess is hidden in romstage_console.c and early_print.h) This patch cleans up the mainboard code to use printk() on all non-ROMCC boards. Change-Id: I2383f24343fc2041fef4af65d717d754ad58425e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8111 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2015-01-06Remove AMD's "Release Content" doxygen from coreboot filesMartin Roth
These comments are left over and are not relevent in the coreboot code, but created a new section titled "Release Content" in the doxygen documentation produced by the coreboot code. In an effort to clean up the output, I'm removing these doxygen comments. Change-Id: I4d7be3313a2ab6c140b4f3afe70dffc4abba7bca Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8069 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-06mainboard/*/romstage.c: Sanitize system header inclusionsEdward O'Callaghan
Fix system include paths to be consistent. Chipset support is part of the Coreboot 'system' and hence 'non-local' (i.e., in the same directory or context). One possible product of this, is to perhaps allow future work to do pre-compiled headers (PCH) on the buildbot for faster build times. However, this currently just makes mainboard's consistent. Change-Id: I2f3fd8a3d7864926461c960ca619bff635d7dea5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8085 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-04AMD Mainboards - PlatformGnbPcie.c: Fix Doxygen errorsMartin Roth
Remove PeiServices param for OemInitEarly - it doesn't exist in the function. Change-Id: I338aeb4128126f6e541815dc09bf8d23678081c8 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8073 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-01-04AMD Mainboards - platform_cfg.h: Fixes for doxygenMartin Roth
- Move @def BIOS_SIZE description to the next line - SB_GEN2 changed to SB_GPP_GEN2 - Move the SIO_HWM_BASE_ADDRESS description to the next line Change-Id: Ia3496b0108484f557627304553461932a100dfa5 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8071 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-20AGESA: Add OemCustomize hooks structureKyösti Mälkki
We should potentially provide an OEM platform hook to manipulate parameters around any entry point to AGESA. Use structure for such ops to avoid weak functions and lots of empty function stubs. Change-Id: I99bf7de8a1e2f183399d2216520a45d0c24fd64c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7824 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA: Ignore error in OemCustomizeInitEarly()Kyösti Mälkki
It does not really matter if we continue or return after a failed assertion, system configuration is invalid anyway. Change-Id: I5ba47ee3fd6c5ff97b9229f8bfc9db08873b08ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7823 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA fam14: Add amd_initenv()Kyösti Mälkki
Not part of wrapper to AGESA, but workaround for enable_resources(). Also remove remains of comments in non-fam14 wrappers. Change-Id: I2526821ca283feb6a506b602b86f817f8b03b341 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7816 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20AGESA: Add amd_initcpuio() and amd_initmmio()Kyösti Mälkki
These are not wrappers for AGESA as they do not enter vendorcode at all. We expect most of the added fixme.c file to be written without use of AMDLIB.h and parts relocated as northbridge enable_resources(). Change-Id: Iba6d59e2a7672349208e9a65fcd2cb1094ab7d50 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7815 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-03AGESA fam14: Move agesawrapper_amdinitmmio()Kyösti Mälkki
Enabling MMCONF PCI-e configuration access should be done before console_init(). This will likely move further to bootblock one day. Change-Id: I20c93fe6e79ef7e7981b2f1cd3c6b446feea0f4e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7163 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-03AGESA: Trace execution with AGESA_EVENTLOG()Kyösti Mälkki
Change-Id: I5601ed92ca808603b0a9edad118ca54aa168aceb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7604 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-03AGESA: Remove duplicate OemCustomizeInitEarly declarationsKyösti Mälkki
Change-Id: I59b2c3f235a6b30e68e78c2fe4065fbc0488bc4c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7158 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-03AGESA fam14: Common agesawrapperKyösti Mälkki
Use copy of amd/persimmon. Change-Id: I7404cb164df9065bcdbaaf5367018870ea675adc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7157 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-03AGESA: Report events with AGESA_EVENTLOG()Kyösti Mälkki
NOTE: For fam12 and fam14 ASSERT() is defined empty so execution may fall through critical failures. Change-Id: Ifef65d749d340f1df3a43b5fcb38c4315ef944e8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7154 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-03AGESA: Use common header for agesawrapperKyösti Mälkki
Change-Id: I5189d0c55635aeb29553fd04a67490cfee3d88d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7153 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-02Replace hlt with halt()Patrick Georgi
There were instances of unneeded arch/hlt.h includes, various hlt() calls that weren't supposed to exit (but might have) and various forms of endless loops around hlt() calls. All these are sorted out now: unnecessary includes are dropped, hlt() is uniformly replaced with halt() (except in assembly, obviously). Change-Id: I3d38fed6e8d67a28fdeb17be803d8c4b62d383c5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7608 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-25agea/family14: Switch to per-device ACPIVladimir Serbinenko
Change-Id: Icc663c28713f2d872bfeb1749303ce92db953bf5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7031 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-22amdfam10: Move to per-device ACPIVladimir Serbinenko
Change-Id: I9ce2333e1ea527843f83d411dea2a669263156c2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7027 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-14AMD: Move RAMBASE and RAMTOPKyösti Mälkki
There are no reasons to not load ramstage @ 0x100000. Boards with HAVE_ACPI_RESUME enabled have performance penalty in using excessive RAMTOP. For these boards, this change releases 11 MiB of RAM from CBMEM allocation to OS. Change-Id: Ib71995aba5e9332d0ec1626b3eb3b4ef6a506d1c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7094 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-07mainboard: Trivial - Make AGESA board include consistentEdward O'Callaghan
Change-Id: If6cb99469f56fff8f88b294b625f0a5205ec540b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7238 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-19AGESA: Drop board and chipset -specific callout headersKyösti Mälkki
Change-Id: If973f28931e65a57cbb8d6739542a57c844f0d66 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7115 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-19AGESA fam12 fam14 fam15: Sanitize BiosCallOuts headersKyösti Mälkki
Change-Id: Ic08f1f2fdbcf6164eb1a0330f9134da3fdb978d7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7114 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-10-19AGESA fam12 fam14 fam15: Use common agesa_readSpd()Kyösti Mälkki
Remove northbridge specific callouts for AGESA_READ_SPD. Move low-level SMBus code to southbridge. Change-Id: I5fc91c49d9ef8e0af1c4d8194f857c61ce417d1d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7113 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-18various AMD boards: fix buffer overflowPatrick Georgi
"AMD\t " isn't 8 characters long. Change-Id: I47b2a39d7dca0201b7ee5dfd1f77e0714411257c Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6991 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
2014-08-15intel/cpu: rename car.h to romstage.hAaron Durbin
This header has nothing to do with cache-as-ram. Therefore, 'car' is the wrong term to use. It is about providing a prototype for *romstage*. Change-Id: Ibc5bc6f3c38e74d6337c12f246846853ceae4743 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/6661 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-14Intel: Add common header file for CAR setupEdward O'Callaghan
When passing '-ffreestanding' the 'main' romstage.c may no longer necessarily be considered the entry point. From the C specification in 5.1.2.1 Freestanding environment; "In a freestanding environment (in which C program execution may take place without any benefit of an operating system), the name and type of the function called at program startup are implementation-defined." Clang complains about these being missing as Clang is somewhat more strict about the spec than GNU/GCC is. An advantage here is that a different entry-point type-signature shall now be warned about at compile time. Change-Id: I467001adabd47958c30c9a15e3248e42ed1151f3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5872 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-06mainboard/amd: De-ASCIIartify AGESA board headersEdward O'Callaghan
As was done for the reference boards in: cd30951 mainboard/amd: De-ASCIIartify reference boards Change-Id: Ie34aa5269388b771daa6934f8aff0314ac6778d5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6290 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2014-07-28AGESA boards: Drop get_bus_conf.c filesKyösti Mälkki
The only remaining purpose for get_bus_conf() was to fill in obscure bus_sb800 (etc.) arrays containing partial PCI bus enumeration. Complete enumeration is available in devicetree and PCI configuration space so discard these arrays. Change-Id: I733115940afba3a50c58aedb9a04ecf5082b1234 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6360 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-28AGESA f14 f15tn 16kb: Move IOAPIC ID setup out of get_bus_conf()Kyösti Mälkki
Change-Id: I7fd14c17242cd3deb7a784fc918ad6fe1191bd13 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6359 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-28AGESA boards: Use devicetree for PCI bus enumerationKyösti Mälkki
Previously MP table contained PCI_INT entries for PCI bus behind bridge 0:14.4 even if said PCI bridge function was disabled. Remove these as invalid, indeterminate bus number could cause conflicts. PCI_INT entries with bus_sb800[2], bus_hudson[2] and bus_yangtze[2] were invalid as there is no PCI bridge hardware on device 0:14.0. Remove these as invalid, indeterminate bus number could cause conflicts. Change-Id: Ie6a3807f64c8651cf9f732612e1aa7f376a3134f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6358 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-28AGESA: Have IRQ routing in mptablesKyösti Mälkki
MP table should be complete with IRQ routing information even when we have ACPI tables. Change-Id: Ieeaed442aea6217f4477b7ac7e06a1926eec8996 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6361 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-28AGESA: Drop some excessive agesawrapper.h includesKyösti Mälkki
Change-Id: I3807912b1dc68fae8248a66e37bbe642fb92d3ae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6262 Tested-by: build bot (Jenkins)
2014-07-24AGESA: Drop offset on PCI device enumerationKyösti Mälkki
Integrated PCI devices in southbridge silicon have static BDFs, no need to have variables to store the parent bus or an offset with constant zero. Change-Id: I37d3794d36b5e5775da9215574ddc199696646d0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6333 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24AGESA: Drop unused extern declarationsKyösti Mälkki
Change-Id: I7f681b40251f49ff717589ed5e7d7e00ee36c7c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6332 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24AGESA boards: Drop global bus_isaKyösti Mälkki
Only ever used as lvalue (except when incrementing) so this global is unused. Change-Id: I616721f937eb0bfdb28f356284efd70f99ccd2dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6330 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24src/mainboard: Remove trailing whitespaceElyes HAOUAS
Change-Id: I14a9dc99acb5d5365a3d7e99a3964120bb611b05 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6308 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24lippert/spacerunner-lx/devicetree.cb: Remove trailing whitespaceElyes HAOUAS
Change-Id: I1a5b5d19ff72b028bbf5bb1c1414eebbf9827a2b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6351 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24lippert/literunner-lx/devicetree.cb: Remove trailing whitespaceElyes HAOUAS
Change-Id: Ib71e25a33e7fe6d43f2ebac0494c263318fa243e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6352 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>