coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-10-21	soc/intel,mb/*: get rid of legacy pad macros	Michael Niewöhner
2020-10-13	{src/mb,util/autoport}: Use macro for DSDT revision	Elyes HAOUAS
2020-10-05	soc/intel/common/block/acpi: Factor out common platform.asl	Subrata Banik
2020-08-08	soc/intel/skylake: Enable CIO depending on devicetree configuration	Felix Singer
2020-08-08	soc/intel/skylake: Enable SDXC depending on devicetree configuration	Felix Singer
2020-08-07	soc/intel/skylake: Enable thermal subsystem depending on devicetree	Felix Singer
2020-07-29	soc/intel/skylake: Enable HDA depending on devicetree configuration	Felix Singer
2020-07-29	soc/intel/skylake: Enable eMMC depending on devicetree configuration	Felix Singer
2020-07-29	soc/intel/skylake: Enable TraceHub depending on devicetree configuration	Felix Singer
2020-07-29	soc/intel/skylake: Enable SMBus depending on devicetree configuration	Felix Singer
2020-07-29	soc/intel/skylake: Enable LAN depending on devicetree configuration	Felix Singer
2020-07-29	soc/intel/skylake: Enable SATA depending on devicetree configuration	Felix Singer
2020-07-26	skylake boards: Factor out copy-pasted PIRQ routes	Angel Pons
2020-05-18	skylake: update processor power limits configuration	Sumeet R Pawnikar
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-02	acpi: Move ACPI table support out of arch/x86 (3/5)	Furquan Shaikh
2020-04-05	fsp2_0: Clean up around `config FSP_USE_REPO`	Nico Huber
2020-03-10	mb/libretrend/lt1000: Add Libretrend LT1000 mainboard	Michał Żygowski