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path: root/src/mainboard/libretrend/lt1000/devicetree.cb
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2024-08-28tree: Use boolean for "eist_enable"Elyes Haouas
Change-Id: I4fc824bef1daf8c12eb671c58de9019ce5a23a2e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2024-07-12skl/kbl mainboards: Move PCIe related settings into their device scopeFelix Singer
Change-Id: I1ffa87eeee521180f37371e5a0d1f9a1a06091aa Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83373 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-06-26skl mainboards/dt: Move serirq setting into LPC device scopeFelix Singer
Change-Id: I84da5365907664ce223dec4adb22a8f1a6e2a144 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83188 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2024-06-26skl mainboards/dt: Move SATA related settings into SATA device scopeFelix Singer
Change-Id: I50706d7a077767d2295d6d5f209c30109d607277 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83179 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-26skl mainboards/dt: Move genx_dec settings into LPC device scopeFelix Singer
Change-Id: Iecb4851bedb7c9ed7793763d80acbcbb068e8832 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83172 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-26skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scopeFelix Singer
Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-06-24skl mainboards/dt: Drop SataPortsDevSlp[x] setting if disabledFelix Singer
The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: I572a9092633c61907794ecbbbe431066d889c5fb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-24skl mainboards/dt: Drop SataSalpSupport setting if disabledFelix Singer
The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: Icb41f0a9baded01267410bd4c9458ab4bfb82b70 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83175 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
2024-06-24skl mainboards/dt: Drop ScsEmmcHs400Enabled setting if disabledFelix Singer
The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: I1239132d5f25345ebb051d216e9187f3d2250339 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83174 Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-24skl mainboards/dt: Drop SsicPortEnable setting if disabledFelix Singer
The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: Ic16d568c38d708da27efa7229e23019e71c0019b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-23skl mainboards: Move cpu_cluster device to chipset devicetreeFelix Singer
Change-Id: I7114612e686a0bf3cfc241f45fa62077fad16f5a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-11-13mb/libretrend/lt1000: Make use of the chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: I6ba850c783999d06c73137ed77d32fc108a20347 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-28mb/{sm/x11,razor,libretrend}/dt: Use comma separated list for arraysFelix Singer
In order to improve the readability of the settings, use a comma separated list to assign values to their indexes instead of repeating the option name for each index. Don't convert the settings for PCIe root ports as they will be moved into the devicetree to their related root ports at some later point. While on it, remove superfluous comments related to modified lines. Change-Id: I27bac17098beb8b6cb3942e68a37da0095f0d0bd Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-01-30mb/*: Remove lapic from devicetreeArthur Heymans
The parallel mp code picks up lapics at runtime, so remove it from all devicetrees that use this codebase. Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-01-16soc/intel/skl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. 3. Make dt CSE PCI device `on` by default. 4. Mainboards set DISABLE_HECI1_AT_PRE_BOOT=y to make Heci1 function disable at pre-boot instead of the dt policy that uses `HeciEnabled = 0`. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-12mainboard: Drop `SataMode` setting from Skylake devicetreesFelix Singer
All Skylake mainboards use the default value for the setting `SataMode`. Thus, drop it from their devicetree. Change-Id: I9be5eca93cac65afc4cc30ceb64d9a5b7e5cd514 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59888 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by defaultFelix Singer
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the default by changing its enum value to 0 and remove its configuration from all related devicetrees. If `common_soc_config.chipset_lockdown` is not configured with something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT` is used. Also, add a release note for the upcoming 4.15 release. Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-12mb/*: drop LPC generic range for port 80Michael Niewöhner
Port 80 (actually 0x80-0x8f) is a fixed I/O range and thus does not have to be set up as generic range. Drop the entries from the devicetrees. Change-Id: I8a54d3c35a321a2d57bd846662f7339eff53e5a8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-14soc/intel/skylake: Drop always-zero ProbelessTrace dt settingAngel Pons
This seems to be a debugging option. Since unset devicetree options default to zero, drop the setting. If it is needed in the future, a user-visible Kconfig option would probably make more sense. Change-Id: I0a71bc407fa92da3dcc0e3dbd666438d4280ffcb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-13soc/intel/{skl,cnl}: replace PM ACPI timer dt option by KconfigMichael Niewöhner
Select `PM_ACPI_TIMER_OPTIONAL` to enable the new PM ACPI Kconfig and set the FSP option for PM ACPI timer enablement from its value instead of using the old devicetree option. Also drop the obsolete devicetree option from soc code and from the mainboards and add a corresponding Kconfig entry instead. Change-Id: I10724ccf1647594404cec15c2349ab05b6c9714f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45955 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`Michael Niewöhner
The dt option `speed_shift_enable` is obsolete now. Drop it. Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-08-08soc/intel/skylake: Enable CIO depending on devicetree configurationFelix Singer
Currently, CIO gets enabled by the option Cio2Enable, but this duplicates the devicetree on/off options. Therefore, depend on the devicetree for the enablement of the CIO controller. All corresponding mainboards were checked if the devicetree configuration matches the Cio2Enable setting, and missing entries were added. Change-Id: I65e2cceb65add66e3cb3de7071b1a3cc967ab291 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44032 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-08soc/intel/skylake: Enable SDXC depending on devicetree configurationFelix Singer
Currently, SDXC gets enabled by the option ScsSdCardEnabled, but this duplicates the devicetree on/off options. Therefore, depend on the devicetree for the enablement of the SDXC controller. All corresponding mainboards were checked if the devicetree configuration matches the ScsSdCardEnabled setting, and missing entries were added. Change-Id: I298b7d0b0fe2a7346dbadcea4be22dc67fce4de8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-07soc/intel/skylake: Enable thermal subsystem depending on devicetreeFelix Singer
Currently SA thermal subsystem gets enabled by the option Device4Enable, but this duplicates the devicetree on/off options. Therefore depend on the devicetree for enablement of the SA thermal subsystem controller. All corresponding mainboards were checked if the devicetree configuration matches the Device4Enable setting, and missing entries were added. Change-Id: I7553716d52743c3e8d82891b2de14c52c6d8ef16 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44026 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29soc/intel/skylake: Enable HDA depending on devicetree configurationFelix Singer
Currently HDA gets enabled by the option EnableAzalia, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the HDA controller. I checked all corresponding mainboards if the devicetree configuration matches the EnableAzalia setting. Change-Id: Id20d023b2f286753fb223050292c7514632e1dd3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43866 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29soc/intel/skylake: Enable eMMC depending on devicetree configurationFelix Singer
Currently eMMC gets enabled by the option ScsEmmcEnabled, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the eMMC controller. I checked all corresponding mainboards if the devicetree configuration matches the ScsEmmcEnabled setting. Change-Id: I3b86ff6e2f15991fb304b71d90c1b959cb6fcf43 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-29soc/intel/skylake: Enable TraceHub depending on devicetree configurationFelix Singer
Currently TraceHub gets enabled by the option EnableTraceHub, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the TraceHub controller. I checked all corresponding mainboards if the devicetree configuration matches the EnableTraceHub setting. Change-Id: Idcd1e5035bc66c48620e4033d8b4988428e63db9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43847 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29soc/intel/skylake: Enable SMBus depending on devicetree configurationFelix Singer
Currently SMBus gets enabled by the option SmbusEnable, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the SMBus controller. I checked all corresponding mainboards if the devicetree configuration matches the SmbusEnable setting. Change-Id: I0d9ec1888c82cc6d5ef86d0694269c885ba62c41 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-29soc/intel/skylake: Enable LAN depending on devicetree configurationFelix Singer
Currently LAN gets enabled by the option EnableLan, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the LAN controller. I checked all corresponding mainboards if the devicetree configuration matches the EnableLan setting. Change-Id: I36347e8e0f0ddba47aec52aeb6bc047e3c8bfaa4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-29soc/intel/skylake: Enable SATA depending on devicetree configurationFelix Singer
Currently SATA gets enabled by the option EnableSata, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the SATA controller. I checked all corresponding mainboards if the devicetree configuration matches the EnableSata setting. Change-Id: I217dcb7178f29bbdeada54bdb774166126b47a5a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-26skylake boards: Factor out copy-pasted PIRQ routesAngel Pons
Put them in common code just in case something depends on the values. Change-Id: Ief526efcbd5ba5546572da1bc6bb6d86729f4e54 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43851 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18skylake: update processor power limits configurationSumeet R Pawnikar
Update processor power limit configuration parameters based on common code base support for Intel Skylake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on nami system Change-Id: Idc82f3d2f805b92fb3005d2f49098e55cb142e45 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-03-10mb/libretrend/lt1000: Add Libretrend LT1000 mainboardMichał Żygowski
Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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