coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2022-01-16	soc/intel/skl: Replace dt `HeciEnabled` by `HECI1 disable` config	Subrata Banik
2021-12-12	mainboard: Drop `SataMode` setting from Skylake devicetrees	Felix Singer
2021-08-28	soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by default	Felix Singer
2021-04-12	mb/*: drop LPC generic range for port 80	Michael Niewöhner
2020-12-14	soc/intel/skylake: Drop always-zero ProbelessTrace dt setting	Angel Pons
2020-11-13	soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig	Michael Niewöhner
2020-10-26	mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`	Michael Niewöhner
2020-08-08	soc/intel/skylake: Enable CIO depending on devicetree configuration	Felix Singer
2020-08-08	soc/intel/skylake: Enable SDXC depending on devicetree configuration	Felix Singer
2020-08-07	soc/intel/skylake: Enable thermal subsystem depending on devicetree	Felix Singer
2020-07-29	soc/intel/skylake: Enable HDA depending on devicetree configuration	Felix Singer
2020-07-29	soc/intel/skylake: Enable eMMC depending on devicetree configuration	Felix Singer
2020-07-29	soc/intel/skylake: Enable TraceHub depending on devicetree configuration	Felix Singer
2020-07-29	soc/intel/skylake: Enable SMBus depending on devicetree configuration	Felix Singer
2020-07-29	soc/intel/skylake: Enable LAN depending on devicetree configuration	Felix Singer
2020-07-29	soc/intel/skylake: Enable SATA depending on devicetree configuration	Felix Singer
2020-07-26	skylake boards: Factor out copy-pasted PIRQ routes	Angel Pons
2020-05-18	skylake: update processor power limits configuration	Sumeet R Pawnikar
2020-03-10	mb/libretrend/lt1000: Add Libretrend LT1000 mainboard	Michał Żygowski