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2019-10-11sb/intel/i82801gx: Move CIR init to a common placeArthur Heymans
Some boards with the G41 chipset lacked programming CIR, so this change add that to those boards too. Change-Id: Ia10c050785170fc743f7aef918f4849dbdd6840e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-09mb/[google/intel/lenovo]/*: fix posix shell bug with SPD filesGreg V
FreeBSD's sh (basic posix shell) did not interpret the '\%o' escape in the same way bash/zsh do. As a result, the decoded files ended up with ASCII numbers instead of the decoded binary data. Change-Id: I95b414d959e5cd4479fcf100adcf390562032c68 Signed-off-by: Greg V <greg@unrelenting.technology> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-08mb/lenovo/t60: Switch to override treePeter Lemenkov
Change-Id: I13c0134b22e2203e6cee6ecafda0dae89e086aff Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34779 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-08mb/lenovo/{t60,z61t}: Convert to variant boardPeter Lemenkov
Change-Id: I0a3076780ac5cf183235f06e4c56d0707bf5e6ca Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-06mb/{lenovo/x201,packardbell/ms2290}: Remove unused ACPI symbolsArthur Heymans
Change-Id: I3a3174cf20cea60d8b2c4d0311a48ce9ffe1a8a1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-10-06nb/intel/nehalem: Move PCH init to sb/intel/ibexpeakArthur Heymans
This change does the following: - Move PCH init code from the common romstage to sb code, this allows for easier reuse in bootblock - Provide a common minimal LPC io decode setup, mainboards can override this in the mainboard_lpc_init if required - Set up LPC generic IO decode up in romstage based on devicetree settings - Remove the ramstage LPC generic IO decode from ramstage as this is now done in romstage.c - Get rid of unneeded setup of spi_read configuration in BIOS_CNTL as this is already done in the bootblock. Change-Id: I3f448ad1fdc445c4c1fedbc8497e1025af111412 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-10-06nb/intel/nehalem: Move romstage boilerplate to a common locationArthur Heymans
Move the mainboard_romstage_entry to a common location and provide mainboard specific callbacks. Change-Id: Ia827053617cead5d2cf8e9f06cb68c2cbb668ca9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-10-06sb/intel/ibexpeak: Don't clear PMBASE regs in romstageArthur Heymans
X201 boots fine without it. Change-Id: I20a8e598b07bf0a059dcb47651d1a26456863673 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35769 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-06sb/intel/ibexpeak: Implement USB current settingsArthur Heymans
This is based on the sandybridge settings. The current lookup table comes from the x201 vendor lookup table. Tested: USB mouse and webcam still work and current registers are the same as before. USB IR are not but the code follows EDS instead of the register replay. Change-Id: Icea9673623a62e7039d5700100a2ee238478abd1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35762 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-06intel/ibexpeak boards: Remove undocumented reset defaults from RCBA replayArthur Heymans
The values read back in those ranges are identical before and after this change and the Lenovo Thinkpad X201 still boots fine. Change-Id: I406510e0573ac97003da7d97181abdfbfd2a872f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35760 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-06intel/ibexpeak boards: Remove handled RCBA entries from replayArthur Heymans
The RCBA registers 0x3400-0x3500 are all handled elsewhere in the code, so no need to have a 'replay' of those. The remainder now consist of USB setup and undocumented bits that should likely not be touched at all. Change-Id: I69fc8a5e16f7cf0e1068d0d2ed678a6c2f6e70a9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-10-06sb/intel/ibexpeak: Implement PCH function disable in chip_opsArthur Heymans
This does the following: - implement a PCH disable function that will be called by the PCI drivers as part of their chip_ops - removes the iobp_x calls as those don't exist on ibexpeak - complete the devicetree with to be disabled PCI devices for the chip_ops to be called - Clean up some code copied from bd82x6x Change-Id: I78d25ffe9af482c77d397a9fdb4f0127e40baddc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-10-06nb/intel/nehalem: Disable PEG and IGD based on devicetreeArthur Heymans
Tested on Thinkpad X201: PEG device hidden. Change-Id: Ib378458a55e18cc02fc49b3e6d6939d31dd4aa65 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35744 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-06sb/intel/ibexpeak: Add CIR initializationArthur Heymans
This properly sets up the chipset initialization registers, instead of replaying an RCBA dump. The information is taken from the EDS and from the thinkpad x201 vendor BIOS disassembly and from an HP UEFI. TESTED on Thinkpad X201. Seems stable at booting, rebooting and resume from S3. Change-Id: I21c2beaf70da27dbe6a56e2612df2c257c05fc62 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-09-28mb/lenovo/x131e: enable mSATA slotJames Ye
Per google/stout. Tested with SanDisk SSD U110. Change-Id: I7cc9837f572236acac2007e95990e64c25a5d6e2 Signed-off-by: James Ye <jye836@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2019-09-27mb/lenovo/x131e: correct USB port configJames Ye
Based on schematic and register dumps. Change-Id: I91fc47022988cfe986fb8c1ed21dc073ee7d16bc Signed-off-by: James Ye <jye836@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-09-17mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controllerBill XIE
Some T430s variants have a Thunderbolt controller wired to PCIe port The controller hotplugs itself to the chipset when a downstream device is hotplugged into it, so the hotplug capability should be enabled on PCIe port #5. TODO: find the correct gpio pin to detect the Thunderbolt controller at runtime. There are 3 variants of mainboard for Thinkpad T430s: Basic type (Wistron LSN-4 11263-1), Boards with an additional discreet GPU, Boards with an additional TB controller (Wistron LSN-4 11271-1), each of which has a different schematic. The gpio27 on the last type is set as set as GPIO-INPUT, compared with GPIO-OUTPUT-HIGH on the basic type boards. Change-Id: I61f41db100f398069e50e2da8a378b3a8d1c84bf Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-17cpu/intel/model_2065x: Don't redefine CPU_ADDR_BITSArthur Heymans
This Kconfig symbol is set at a default of 36 in cpu/x86 and is now only used in the romcc bootblock to set up caching to upgrade the microcode. It's not mainboard specific. Change-Id: I29d3a8308025e586a823603f8d6edafd30cb9d95 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35436 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-17nb/nehalem: Move MMCONF_BASE_ADDRESS to a common placeArthur Heymans
Change-Id: I872959c4a38e28c29220b81c9fe029e7fc553ccf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35435 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15mb/*/{x201,ms2290}/mainboard.c: Remove superfluous ramstage codeArthur Heymans
Change-Id: I0270c50dea2a2ce6c8e6114ed708f06be9d33c0e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-28lenovo/t431s,w530: Add DRIVERS_RICOH_RCE822Kyösti Mälkki
Device is present in devicetree but not included in the build. Change-Id: I8555d94902e94c623d8fbe6f1a4ffe7637988530 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-26soc/intel: Use common romstage codeKyösti Mälkki
This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to <arch/romstage.h>. Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20mb,autoport: Fix GCC 9 Port_List build errorJacob Garber
Port_List is an array of 8 elements, and GCC 9 is warning that there are no 'others' when all 8 elements are explicitly initialized, which is causing the build to fail. Remove the 'others => Disabled' clause to silence this. Change-Id: Id082e7a76641438f3fb4c4d976dbd254a7053473 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34918 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-18cpu/intel: Enter romstage without BISTKyösti Mälkki
When entry to romstage is via cpu/intel/car/romstage.c BIST has not been passed down the path for sometime. Change-Id: I345975c53014902269cee21fc393331d33a84dce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-18mainboards: Remove floating __PRE_RAM__ commentsKyösti Mälkki
Change-Id: I110e54175a81b6a651213e0f18ddc1e3e71160cf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-07-19sb/intel/{bd82x6x|ibexpeak}: Drop p_cnt_throttling_supportedPatrick Rudolph
The processor P_BLK doesn't support throttling. This behaviour could be emulated with SMM, but instead just update the FADT to indicate no support for legacy I/O based throttling using P_CNT. We have _PTC defined in SSDT, which should be used in favour of P_CNT by ACPI aware OS, so this change has no effect on modern OS. Drop all occurences of p_cnt_throttling_supported and update autoport to not generate it any more. Change-Id: Iaf82518d5114d6de7cef01dca2d3087eea8ff927 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-18mb/*/*/gpio: Use static for const structuresPeter Lemenkov
Autoport generates these structures as static so let's make it consistent. See also commit 128205fd with Change-Id I83382d38a4a3b7ed11b8e7077cc5fbe154e261a7 ("autoport/bd82x6x.go: Improve gpio.c generation"). Change-Id: I4e07bd755ca4a65b76c69625d235a879fe7b43cb Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33524 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13intel/i945: Fix udelay() prototypesKyösti Mälkki
Change-Id: Ia157c6417bdd9c4ffbdf07683c51d0680e9356c9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-09arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-classKyösti Mälkki
Build of the entire smm-class is skipped if we have HAVE_SMI_HANDLER=n. Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-08sb/intel/ibexpeak: Use common final SPI OPs setupArthur Heymans
This also removes the relevant RCBA replays the mainboard dir. Change-Id: I75dd9d1bcd09d835f205a51c087d52ebb4e166f6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Thomas Heijligen <src@posteo.de>
2019-07-07mb/lenovo/g505s: Disable SeaBIOS options unsupported by hardwareMike Banon
G505S doesn't have any SAS or NVMe controllers and couldn't have a TPM, so it makes sense to disable the related SeaBIOS options for this board. This reduces the size of compiled SeaBIOS by 129344-110048=19296 bytes. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: Ib0183b7786ecd77bb0df923bc84908275f2fe14c Reviewed-on: https://review.coreboot.org/c/coreboot/+/33870 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07mb/lenovo/t60: Align ACPI C-state across the similar boardsPeter Lemenkov
We have 3 similar Lenovo mainboards - x60 (oldest), t60, and z61t (most recent addition). The only one with two consequent 2s as the C-types is t60: static acpi_cstate_t cst_entries[] = { { 1, 1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } }, { 2, 1, 500, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 } }, { 2, 17, 250, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } }, }; It seems that 3 could be a better choice for the last line here. UNTESTED on a real hardware. Change-Id: I090e82d5f4ae25c768ff45a01a8dd76ff8a96a90 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-25intel/945 boards: Use smp_write_pci_intsrc()Kyösti Mälkki
Radically reduces line lengths and splits '(bus<<2) | INT' to separate parameters. Change-Id: I0cfd714da3d2773affdb34d1dab2ac32879e2cfd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30740 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-25mb/lenovo/z61t: Remove `fn_ctrl_swap` optionPeter Lemenkov
It seems that the EC on t60/x60/z61t doesn't support it. This wasn't even introduced in z61t so let's remove the remaining bits. This commit follows up on commit a5fcc2e4 with Change-Id Id2964002406a5fcf992f0ffc3627e3f66a2bb13f ("mb/lenovo/x60/t60: Remove `fn_ctrl_swap` option"). Tested on a real hardware. Change-Id: Ifd5e7823af305cc4a0194ee2097a749e43680c55 Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Andrey Korolyov <andrey@xdel.ru>
2019-06-21mb/lenovo/x201: Remove duplicated includePeter Lemenkov
Change-Id: I0917f11091b8c93c21c0e25690440b7dd0e9c8ba Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-06-21sb/intel/bd82x6x: Set up io_gen_dec in romstage based on devicetreeArthur Heymans
Set up generic decode ranges based on the devicetree settings. Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-21mb/lenovo/x201/smihandler.c: Remove useless smihandler codeArthur Heymans
This code to handle the brightness from SMM is copied from the Lenovo Thinkpad X60 code, but does not work on later generation. The PCI device it tries to address does not even exist on those devices. Change-Id: I0c25c3e5bec651b27158a84cc91289639a04ceb6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-21mb/*/{x201,packardbell}: Remove unused C-state generation functionsArthur Heymans
Those are copied from Lenovo X60 code, but are unused. NOTE: No ACPI C-state are generated on this platform but Linux has a separate driver for that. Change-Id: Ie9b49f5451d8cde9c36672cac1f0f14cb3f0095e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33140 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21sb/intel/ibexpeak/smihandler: Move finalizing to a common locationArthur Heymans
TODO: There is no reason to do this in SMM. Change-Id: I8bbb2f65bbe674bd1bc4ae8a4086bd1f5e9a79fa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33139 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-19{mb,sb}: Use get_acpi_table_revision(FADT)Elyes HAOUAS
Change-Id: Id3d7f021a52e08906ae0a3f794756e397601fe96 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33428 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-19mb/lenovo/*/romstage: Remove unused include byteorder.hPeter Lemenkov
Change-Id: I3e500aafd26b7524a6782883b9a30f55b544102d Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33511 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-19mb/lenovo/z61t/romstage: Remove unused includePeter Lemenkov
This commit follows up on commit commit 89989cf6 with Change-Id: I1f44ffeb54955ed660162a791c6281f292b1116a ("src: Drop unused include <arch/acpi.h>"). Change-Id: I3dc12373b32b95d25ba7b302cbca5f927678315d Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33365 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-19mb/lenovo/t60/romstage: Remove unused includePeter Lemenkov
This commit follows up on commit 8b7a1614 with Change-Id: I73c557d6ef009fb2cac35fdea500dee76f525330 ("src/mainboard: Remove unneeded include <arch/io.h>"). Change-Id: I7f307bf5b6cdcfebe1a290ce344b962fcecc8781 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-06-19mb/lenovo/x201: Remove unneeded includesPeter Lemenkov
Tested: still builds fine. Change-Id: I1ca4e42bd75a3e84afe8b30a60f02058b590416f Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-06-16mb/lenovo/*/smihandler: Remove unused includePeter Lemenkov
All usage of pci_read_config8 was removed in commit d44d4f0f with Change-Id Ia959eb5b747846048396e66d4c926c96c27f3878 ("mb/lenovo/*: Remove useless smihandler code"). So we don't need this include anymore. Change-Id: Ic4f038c80e17799016ae7e92a5675cfe7c71e400 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-06-14nb/i945: Drop CHANNEL_XOR_RANDOMIZATION selectionElyes HAOUAS
CHANNEL_XOR_RANDOMIZATION is configurable for no reason. Change-Id: I31e6ed6cb040dcba756cbfd2247d90753d372915 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-08mb/lenovo/t430: Fix Dual GraphicsPatrick Rudolph
* Select ONBOARD_VGA_IS_PRIMARY in driver/lenovo/hybrid_graphics to fix disabling iGPU in 'Dual Graphics' on Lenovo T430. * Remove ONBOARD_VGA_IS_PRIMARY in mainboards that already select DRIVERS_LENOVO_HYBRID_GRAPHICS. Change-Id: I6594fbb957c9a8135fe670d38b5755adf29d2dff Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-06sb/intel/i82801gx: Detect if the southbridge supports AHCIArthur Heymans
This automatically detects whether the southbridge supports AHCI. If AHCI support is selected it will be used unless "sata_no_ahci" is set in the devicetree to override the behavior. Change-Id: I8d9f4e63ae8b2862c422938f3103c44e761bcda4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-05sb/intel/i82801gx: Include chip.h directlyArthur Heymans
Change-Id: I3d743e90444292be687999ab4f50aa89d514fbad Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33171 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-05mb/*/devicetree.cb: Remove unavailable PCIe portsArthur Heymans
Some variants only support 4 PCIe ports so there is no need to have those unavailable ports in the devicetree. Change-Id: I154cae358fb7f862fc0c8eaa620474b37b5e6484 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30821 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03mb/lenovo/*: Remove useless smihandler codeArthur Heymans
This code to handle the brightness from SMM is copied from the Lenovo Thinkpad X60 code, but does not work on later generation. The PCI device it tries to address does not even exist on those devices. Change-Id: Ia959eb5b747846048396e66d4c926c96c27f3878 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33138 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-30mb/lenovo/*20*: Remove default FMAPNico Huber
These boards don't need a default FMAP. Moreover, having a default FMAP disables automatic integration of optional regions like `CONSOLE`. Also, these files contain an error: `COREBOOT` isn't placed at the top of the image. Resulting in default builds without a reset vector ;) Change-Id: If6331e19955034c02828e88902a5934c34d3e784 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33110 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29src/mainboard: Add missing 'include <types.h>'Elyes HAOUAS
<types.h> is supposed to provide <stdint.h> and <stddef.h>. So when <types.h> is included, <stdint.h> and/or <stddef.h> is removed. Change-Id: I3b1a395cfe8b710fb6b468e68f4c92e063794568 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-27sb/intel/ibexpeak: Use common Intel SMM codeArthur Heymans
TODO in followup patch: Some not mainboard specific things should be moved out of mainboard_smi_apmc. Change-Id: Ifc2d8f7755ace598e66b162d071d472093e4656e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-25mb/lenovo: Unify thermal threshold handlingPeter Lemenkov
Unify thermal handling across Lenovo boards (except g505, which is different). Namely, do the following: * Move thermal levels from acpi_tables to thermal.h (and create if necessary). * Don't use board-specific ifdef guards. * Set thermal levels using dedicated acpi_update_thermal_table function as almost all Lenovo boards do. * Update list of authors in comments. Merge all author's entries. * Minor whitespace and formatting. This makes diff -ruw between the Lenovo boards smaller. Change-Id: If569f67c932b7fbf14893b890a5588df4994daeb Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29659 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-21mb/lenovo/r500: Add mainboardArthur Heymans
Tested: - Ethernet NIC - Wifi RFKill - USB - LVDS, VGA with libgfxinit - Booting with dock attached (COM1) - Keyboard, trackpoint - SeaBIOS 1.12 - S3 resume - Tested in descriptor mode, with vendor FD and ME - Add VBT to ACPI OPregion Untested: - SATA (likely works) - Trackpad (my cable is broken, likely works) - Displayport (likely works) - Descriptorless mode - DVD drive - Extra battery - model with ATI GPU Does not work: - Dock hotplug - Quad core CPU (hangs during AP init, probably needs hardware mod) - Hotplugging the expresscard slot (works with 'echo 1 | sudo tee /sys/bus/pci/rescan') TODO: - proper dock support - documentation note: This board was hard to flash, I had to desolder the flash. TESTED: on a R500 with an Intel iGPU, SeaBIOS 1.12, Debian 9, Linux 4.9 from USB Change-Id: I9e129b2e916acdf2b8534fa9d8d2cfc8f64f5815 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/28644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-21mb/lenovo/t400: Add VBT fileArthur Heymans
All variants (t400, r400, t500, w500) use the same OPROM for the IGD. Change-Id: I1b9db7b29b22809542f80f60a5e2eb3283fe1c02 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-15src/mainboard: Remove unneeded include <arch/io.h>Elyes HAOUAS
Change-Id: I73c557d6ef009fb2cac35fdea500dee76f525330 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-14mb/{lenovo/x201,packardbell/ms2290}: Remove superfluous TS initArthur Heymans
Timestamps are initialized in cpu/intel/car/romstage.c. Change-Id: Ia2b762667be17aa5b482cd585dd6f6198cf50d9e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32758 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-13mb/lenovo/s230u: Rewrite trigger inversion ACPI codeMartin Roth
The GPIO invert registers are already defined in the PCH code, so just use the 8-bit versions of the registers instead of creating a new GPIO field for the single bits. This allows us to get rid of the Field(GPIO...) code that's causing problems with IASL version 20190509. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Iac5dfb71b3a2b5a25c05a403cf5f403c7acecaaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/32753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-05-13mb/t400/acpi: Update ATPR buffer to fit all entriesElyes HAOUAS
Error spotted using acpica version 20190509 (Change-Id: I6779a20). Change-Id: Ic9cf16a7494667f6dab156c697fb8f8e9966051e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-12nb/intel/snb: Drop NORTHBRIDGE_INTEL_IVYBRIDGENico Huber
We keep the support, though. Just now that `libgfxinit` is fixed, we don't need the distinction anymore. Causally, we also don't need CPU_INTEL_MODEL_306AX any more. TEST=Played tint on kontron/ktqm77. Score 606 Change-Id: Id1e33c77f44a66baacba375cbb2aeb71effb7b76 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-12mb/lenovo/*: Add MAINBOARD_FAMILYPatrick Rudolph
The Kconfig MAINBOARD_FAMILY sets the family field of SMBIOS entry 1. Match what vendor firmware does and use the same value as in the version field. Required for fwupd which uses the family field to generate a GUID. Change-Id: I0033c42c5eac6b9d47d0acd16c67467b6d419534 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-05-08mb/lenovo/t520: Fix devicetreePatrick Rudolph
Disable unused PCI devices. Reduces idle power by around 0.5Watt. Tested on Lenovo T520. Change-Id: I6990dc5810084261b75d2a327b6a103be44fd4cc Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-08mb/lenovo/*: Add support for VBOOT on 8MiB devicesPatrick Rudolph
Enable VBOOT support on all devices that have a 8 MiB flash, using a single RW_MAIN_A partition, allowing the use of tianocore payload in both RW_MAIN_A and WP_RO. * Add VBNV section to cmos.layout * Add FMAP for VBOOT and regular boot * Select Kconfigs for VBOOT * Enable VBOOT_SLOTS_RW_A by default Also build test VBOOT on Lenovo T420. Tested on Lenovo T520 using Icb7b263ed86551cc53e1db7babccaca6b3ae2fe6. Change-Id: Icb7b263ed86551cc53e1db7babccaca6b3ae2fe6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-07mb/lenovo: Add SMBIOS type 9 for ExpressCardPatrick Rudolph
Mark all known PCIe root ports as ExpressCard slot. Tested on Lenovo T520. Change-Id: I43fb481512a54ee054c6fd0189053028fb3c3ec2 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32309 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-07mb/lenovo/x60: Use system_reset()Elyes HAOUAS
Change-Id: I4515d8d14629741f3bf49e9459d7d57c18d321ce Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-06src: Remove unused include <halt.h>Elyes HAOUAS
Change-Id: I2f142cc80692e60eb0f81f57339a247f6ef4a524 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-29src/mb: Use system_reset()Elyes HAOUAS
Use already defined system_reset() function. Change-Id: I68ff4cffa2bfab6a15299795c3e1837fc9b85806 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-19src/mb/Kconfig: Fix PCI subsystem IDsElyes HAOUAS
References to MAINBOARD_PCI_SUBSYSTEM_{DEVICE_ID,VENDOR_ID} were removed in commits dbd3132 sb/intel/{i82801g/i/j,bd82x6x}: Make use of generic set_subsystem() 00bb441 sb/intel/lynxpoint: Remove PCI bridge function Change-Id: I72bba8406eea4a264e36cc9bcf467cf5cfbed379 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32107 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-13sb/intel/i82801gx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIBPatrick Rudolph
Use common code to detect ACPI S3. Tested on Thinkpad X60. Change-Id: Ia759a9ed141efc8130860300f2a8961f0c084d70 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-06src: Use include <delay.h> when appropriateElyes HAOUAS
Change-Id: I23bc0191ca8fcd88364e5c08be7c90195019e399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-03-27Move calls to quick_ram_check() before CBMEM initKyösti Mälkki
After raminit completes, do a read-modify-write test just below CBMEM top address. If test fails, die(). Change-Id: I33d4153a5ce0908b8889517394afb46f1ca28f92 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-24nb/intel/i945: Use DEBUG_RAM_SETUPKyösti Mälkki
Avoid preprocessor here, also we never set loglevel to value of >8 so the call would not be made. The calls to ram_check() were removed, for a long time that function has not tested start..stop region. Change-Id: Ib952b8905c29a5c5c289027071eb6ff59aaa330b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
Drop 'include <string.h>' when it is not used and add it when it is missing. Also extra lines removed, or added just before local includes. Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-18mb/(ICH7): Remove initialization already done at early_init.cElyes HAOUAS
V1CAP is a write-once register, and it is already programmed in intel/i945/early_init.c. Tested on 945G-M4 board (i945G + 82801GB). Change-Id: I4469cb7505d584f10c98aec579a2d78bf1950bf3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-14mb/lenovo/x1_carbon_gen1/cmos: Port USB Always OnPatrick Rudolph
Port commit f1395d82: "ec/lenovo/h8: Add USB Always On" to the Thinkpad x1_carbon_gen1 board as well, as it seems to work fine on all generations. See also commit 7ffb329f with Change-Id I6dcbfaae2a444d9a679ecb64a87dc2a59b8fd281 ("mb/lenovo/*/cmos: Port USB Always On"). Note that we don't need to call h8_usb_always_on() directly since commit 4f4322dd with Change-Id If812cd1ef8fb1a24d7fadbe834f574b40cbcd56a ("lenovo/h8,thinkpads: Re-do USB Always On"). Change-Id: Ib9070b659b0c9ad5dde4200ec2845c6fa2b78b25 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicola Corna <nicola@corna.info>
2019-03-14mb/lenovo/x1_carbon_gen1/acpi: call MUTE(1) and USBP(0) on _PTSNicola Corna
Like with any other Thinkpad, call MUTE(1) and USBP(0) on _PTS on the Lenovo Thinkpad X1 Carbon 1st generation. Without MUTE(1) the speakers sometimes glitch before going into S3 (if not muted), while without USBP(0) the USB ports are always powered in S3, regardless of the USB Always-On mode selected. Change-Id: I86f3c5a72e2589c5570303bf68f39df3ef874cb8 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-13src/mainboard/*/*/cstates.c: Drop unused includesElyes HAOUAS
Change-Id: I315721d6261e558c3f7145c80714262052ce0e49 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31783 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-13{mb,nb/pineview}/*.asl: Remove unneeded include i82801gx.hElyes HAOUAS
Change-Id: I1a0eed712e489b0fb63a7b650151646a56852d76 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30321 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-12src: Drop unused 'include <arch/acpigen.h>'Elyes HAOUAS
Use <arch/acpi.h> when appropriate. Change-Id: I05a28d2c15565c21407101e611ee1984c5411ff0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-07src: Drop unused include <timestamp.h>Elyes HAOUAS
Change-Id: I7e181111cd1b837382929071a350b94c3afc1aaa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-06src: Drop unused include <arch/acpi.h>Elyes HAOUAS
Change-Id: I1f44ffeb54955ed660162a791c6281f292b1116a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-06ec/lenovo/h8: Implement ACPI methods to set battery thresholdsAlexey Kharlamov
There are two known reverse-engineered ways to manage battery thresholds. This patch implements them and adds a way to enable them for different mainboards. Tested on W530 with 4.18.3-gentoo kernel and X220 with 4.20.11. Works fine with new Linux userspace API for controlling battery thresholds, available since 4.17. (/sys/class/power_supply/BAT0/charge_(start|stop)_threshold). The new API is supported by TLP (you might need to set NATACPI_ENABLE=1 in /etc/tlp.conf). tpacpi-bat works fine too. Signed-off-by: Alexey Kharlamov <der@2-47.ru> Signed-off-by: Evgeny Zinoviev <me@ch1p.com> Change-Id: I2a90f9e9b32462b8a5e9bc8d3087ae0fea563ea5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/23178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-04device/pnp: Add header files for PNP opsKyösti Mälkki
Change-Id: Ifda495420cfb121ad32920bb9f1cbdeef41f6d3a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31698 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
Change-Id: I91158452680586ac676ea11c8589062880a31f91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31692 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04arch/io.h: Add missing includesKyösti Mälkki
Fixes indirect includes that would break with followup work. Change-Id: I37ca01b904a0b422a4d09475377e755e167a6ab3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-04arch/x86/acpi: Remove obsolete acpi_gen_regaddr resv fieldElyes HAOUAS
Since ACPI v2.c, this field is access_size. Currently, coreboot is using ACPI v3,so we can drop '.resv' field. Change-Id: I7b3b930861669bb05cdc8e81f6502476a0568fe0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-01device/pci: Fix PCI accessor headersKyösti Mälkki
PCI config accessors are no longer indirectly included from <arch/io.h> use <device/pci_ops.h> instead. Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-01ACPI: Rename FADT model and set it to zeroElyes HAOUAS
INT_MODEL defined in ACPI 1.0 and renamed to reserved since V 2.0. The value for this field is zero but 1 is allowed to maintain compatibility with ACPI 1.0. So set this value to zero as we are using greater version than ACPI 1.0. Change-Id: I910ead4e5618c958a7989f4c309a3a4bb938e31a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29986 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Guckian Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28cpu/intel: Rename socket_mPGA478MN to socket_pNico Huber
These marketing names are much easier to distinguish. My mnemonic: Socket M => up to Merom, Socket P => up to Penryn. Change-Id: I3c2a59596cf7f3cd763bd79962ad326ab080677b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31645 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28cpu/intel: Rename socket_mFCPGA478 to socket_mNico Huber
The name was wrong. mFCPGA478 is actually a pseudonym for mPGA478MN, the successor of the socket that was meant. The official name of this socket is mPGA478MT. But "Socket M" is much easier to distinguish. Change-Id: I4efeaca69acddfcdc5e957b0b521544314d46eeb Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-21ACPI: Correct asl_compiler_revision valueElyes HAOUAS
Change-Id: I91b54b43c8bb5cb17ff86a6d9afa95f265ee49df Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-15src: Use macro `ACPI_FADT_LEGACY_FREE`Paul Menzel
Replace all instances, where 0 is used by the macro/define `ACPI_FADT_LEGACY_FREE`. Change-Id: I226b334620e0cdafc7639c7a76ea3a523ae53a74 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/31289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-02-12nb/intel/nehalem: Remove CAR_GLOBAL useArthur Heymans
We have NO_CAR_GLOBAL_MIGRATION now. Change-Id: I077f235029e3fe3b1368f028981985895d8b766b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30505 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-08mb/*/*/romstage: curly braces after the function definitionPeter Lemenkov
See Documentation/coding_style.md, specifically "Placing Braces and Spaces" section. Change-Id: Ia6a2f3d3547c16500996260b0ece9ec693f00113 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/31268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-07src: Remove unused include device/pnp_def.hElyes HAOUAS
Change-Id: Ibb7ce42588510dc5ffb04c950c4c8c64e9a2fa37 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-02-06nb/intel/gm45: Use a common romstageArthur Heymans
This moves a lot of the common romstage boilerplate code to a common location, while adding a few mainboard specific hooks. Another difference is that the settings for enable_igd and enable_peg are now based on the static devicetree settings. Change-Id: I30ef7f6962aabde78b5c40e0b53bb85e01c254c1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-02-06mb/lenovo/x200/gpio.c: Unclutter the codeArthur Heymans
Some settings don't make sense like specifying input/output on native ports or high/low on input ports. Change-Id: Ib37837b9cdb8bb05e2523e0c43cc71fe4fbf243b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31187 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 22:42:17 +0000