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coreboot.git
macbookair5_2
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master
mbp101_medisable
mbp101_medisable_1
mbp82
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path:
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src
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mainboard
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lenovo
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x220
/
romstage.c
Age
Commit message (
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Author
2016-02-18
southbridge/intel/bd82x6x: Use common gpio.c
Patrick Rudolph
2016-02-12
Merge sandy/ivybridge romstage flow for MRC and non-MRC.
Vladimir Serbinenko
2016-02-09
ivy: Add a possiblity for mainboard early init.
Vladimir Serbinenko
2016-01-10
lenovo/x220: Enable USB 3 controller
Marian Tietz
2015-10-31
tree: drop last paragraph of GPL copyright header
Patrick Georgi
2015-05-21
Remove address from GPLv2 headers
Patrick Georgi
2015-01-06
mainboard/*/romstage.c: Sanitize system header inclusions
Edward O'Callaghan
2014-11-23
sandy/ivy/nehalem: Remerge interrupt handling
Vladimir Serbinenko
2014-10-24
sandy/ivy native: dedup romstage.c main()
Vladimir Serbinenko
2014-10-20
x220: Move to common gpio.h inrastructure
Vladimir Serbinenko
2014-10-17
bd82x6x: Consolidate early native USB init
Vladimir Serbinenko
2014-10-16
x220, x230: Remove unused headers.
Vladimir Serbinenko
2014-10-16
bd82x6x: Move common bd82x6x S3 detect to bd82x6x code.
Vladimir Serbinenko
2014-10-16
sandybridge: Move common northbridge finalize to northbridge code.
Vladimir Serbinenko
2014-08-30
lenovo/x220: New port
Vladimir Serbinenko